FX929A Datasheet, PDF (22/44 Pages) CML Microcircuits – 4-Level FSK Modem Data Pump

4-Level FSK Modem Data Pump
FX929A
1.5.5.3 Control Register
This 8-bit write-only register controls the modem's symbol rate, the response times of the receive clock
extraction and signal level measurement circuits and the Frame Sync pattern recognition tolerance.
Control Register B7, B6: CKDIV - Clock Division Ratio
These bits control a frequency divider driven from the clock signal present at the XTALN pin, and hence
determine the nominal symbol rate. The table below shows how symbol rates of 2400/4800/9600 symbols/sec
may be obtained from common Xtal frequencies:
Division Ratio:
B7 B6 Xtal Frequency/Symbol Rate
00
512
01
1024
10
2048
11
4096
Xtal Frequency (MHz)
2.4576
4.9152
9.8304
Symbol Rate (symbols/sec)
4800
2400
9600
4800
2400
9600
4800
2400
Note: Device operation is not guaranteed below 2400 or above 9600 symbols/sec.
Control Register B5, B4: FSTOL - Frame Sync Tolerance
These two bits have no effect in transmit mode. In receive mode, they define the maximum number of
mismatches which will be allowed during a search for the Frame Sync pattern:
B5 B4
00
01
10
11
Mismatches allowed
0
2
4
6
Note: A single 'mismatch' is defined as the difference between two adjacent symbol levels, thus if the symbol
'+1' were expected, then received symbol values of '+3' and '-1' would count as 1 mismatch, a received symbol
value of '-3' would count as 2 mismatches. A setting of '4 mismatches' is recommended for normal use.
Control Register B3, B2: LEVRES - Level Measurement Modes
These two bits have no effect in transmit mode. In receive mode they set the 'normal' operating mode of the
received signal amplitude and dc offset measuring circuits (the automatic sequencing of an AQLEV command
may temporarily override the 'normal' setting).
© 1996 Consumer Microcircuits Limited
22
D/929A/4