FX929A Datasheet, PDF (28/44 Pages) CML Microcircuits – 4-Level FSK Modem Data Pump

4-Level FSK Modem Data Pump
FX929A
CRC1
This is a sixteen-bit CRC check code contained in bytes 10 and 11 of the Header Block. It is calculated by the
modem from the first 80 bits of the block ( Bytes 0 to 9 inclusive) using the generator polynomial:
x16 + x12 + x5 + 1
CRC2
This is a thirty-two-bit CRC check code contained in bytes 8 to 11 of the 'Last' Block. It is calculated by the
modem from all of the data and pad bytes in the Intermediate Blocks and in the first 8 bytes of the Last Block
using the generator polynomial:
x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1
Note: In receive mode the CRC2 checksum circuits are initialised on completion of any task other than NULL or
RILB. In transmit mode the CRC2 checksum circuits are initialised on completion of any task other than NULL,
TIB or TLB.
Forward Error Correction
In transmit mode, the FX929A uses a Trellis Encoder to translate the 96 bits (12 bytes) of a 'Header',
'Intermediate' or 'Last' Block or the 30 bits of a Station ID Block into a 66 or 22-symbol sequence which
includes FEC information.
In receive mode, the FX929A decodes the received 22 or 66 symbols of a block into 30 or 96 bits of binary data
using a 'Soft Decision' Viterbi algorithm to perform decoding and error correction.
Interleaving
The 66 symbols of a 'Header', 'Intermediate' or 'Last' block are interleaved by the modem before transmission
(and before the 'S' symbols are added) to give protection against the effects of noise bursts and short fades.
The 22 symbols of a 'Station ID' Block are not interleaved.
In receive mode, the FX929A de-interleaves the received symbols after stripping out the 'S' symbols and prior
to decoding.
© 1996 Consumer Microcircuits Limited
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D/929A/4