FX929A Datasheet, PDF (21/44 Pages) CML Microcircuits – 4-Level FSK Modem Data Pump

4-Level FSK Modem Data Pump
FX929A
Modem Rx input
Symbols to
De-interleave circuit
for task #1
t3
for task #2
t3
for task #3
t3
Data from Data Block Buffer
Task to Command Register
BFREE bit
1
t6
1
t6
2
2
3
t6
3 _t7
t7
t7
Figure 11 Receive Task Timing Diagram
t3 Time to receive all symbols of task
t6 Maximum time between first symbol of task
entering the de-interleave circuit and the
task being written to modem.
t7 Maximum time from the last bit of the task
entering the de-interleave circuit to BFREE
going to a logic '1' (high)
Task
SFS
SFP
RSID
RHB/RILB
R4S
SFS
SFP
RSID
RHB/RILB
R4S
Any
Time
(symbol times)
25 (minimum)
48 (minimum)
23
69
4
21
21
15
51
3
1
RRC Filter Delay
The previous task timing figures are based on the signal at the input to the RRC filter (in transmit mode) or the
input to the de-interleave buffer (in receive mode). There is an additional delay of about 8 symbol times through
to the RRC filter in both transmit and receive modes, as illustrated below:
Tx Symbol to RRC Filter
Tx Symbol at Txop pin / Rx Symbol from FM discriminator
Rx Symbol t o D e-int erleave Buffer
Symbol-times
Figure 12 RRC Low Pass Filter Delay
© 1996 Consumer Microcircuits Limited
21
D/929A/4