FX929A Datasheet, PDF (27/44 Pages) CML Microcircuits – 4-Level FSK Modem Data Pump

4-Level FSK Modem Data Pump
FX929A
In receive mode, the FX929A continually measures the 'quality' of the received signal, by comparing the actual
received waveform over the previous 64 symbol times against an internally generated 'ideal'.
The result is placed into bits 3-7 of the Data Quality Register for the µC to read at any time, bits 0-2 being
always set to '0'. Figure 14 shows how the value (0-255) read from the Data Quality Register varies with
received signal-to-noise ratio:
250
200
150
DQ
100
50
0
5
7
9
11
13
15
S/N dB (noise in 2* symbol-rate bandwidth)
Figure 14 Typical Data Quality Reading vs S/N
The Data Quality readings are only valid when the modem has successfully acquired signal level and timing
lock for at least 64 symbol times. It is invalid when an AQSC or AQLEV sequence is being performed or when
the LEVRES setting is 'Clamp' or 'Lossy Peak Detect'. A low reading will be obtained if the PLLBW bits are set
to 'Wide' or if the received signal waveform is distorted in any significant way.
1.5.6 CRC, FEC and Interleaving
Cyclic Redundancy Codes
CRC0
This is a six-bit CRC check code used in the Station ID Block. It is calculated by the modem from the first 24
bits of the block ( Bytes 0,1 & 2) as follows:
The 24 bits are considered as the coefficients of a polynomial M(x) of degree 23, such that the msb bit (7) of
byte 0 is the coefficient of x23, and bit 0 of byte 2 is the coefficient of x0.
The polynomial F(x) of degree 5 is calculated as being the remainder of the modulo-2 division
x6M(x) / (x6 + x4 + x3 + 1 )
The polynomial x5 + x4 + x3 + x2 + x1 + x0 is added (modulo-2) to F(x)
The coefficients of F(x) are placed in the 6-bit CRC0 field, such that the coefficient of x5 corresponds to the
msb of CRC0.
© 1996 Consumer Microcircuits Limited
27
D/929A/4