FX929A Datasheet, PDF (26/44 Pages) CML Microcircuits – 4-Level FSK Modem Data Pump

4-Level FSK Modem Data Pump
FX929A
In receive mode, the BFREE bit is set to '1' (also setting the Status Register IRQ bit to '1') by the modem when
it has completed a task and any data associated with that task has been placed into the Data Block Buffer. The
µC may then read that data and write the next task to the Command Register.
The BFREE bit is also set to '1' - but without setting the IRQ bit - by a RESET task or when the Mode Register
TXRXN or PSAVE bits are changed.
Status Register B5: IBEMPTY - Interleave Buffer Empty
In transmit mode, this bit will be set to '1' - also setting the IRQ bit - when less than two symbols remain in the
Interleave Buffer. Any transmit task written to the modem after this bit goes to '1' will be too late to avoid a gap
in the transmit output signal.
The bit is also set to '1' by a RESET task or by a change of the Mode Register TXRXN or PSAVE bits, but in
these cases the IRQ bit will not be set.
The bit is cleared to '0' within one symbol time after a task other than NULL or RESET is written to the
Command Register.
Note: When the modem is in transmit mode and the Interleave Buffer is empty, a mid level (half-way between
'+1' and '-1') signal will be sent to the RRC filter.
In receive mode this bit will be '0'.
Status Register B4: DIBOVF - De-Interleave Buffer Overflow
In receive mode this bit will be set to '1' - also setting the IRQ bit - when a RHB, RILB, RSID or R4S task is
written to the Command Register too late to allow continuous reception.
The bit is cleared to '0' immediately after reading the Status Register, by writing a RESET task to the Command
Register or by changing the TXRXN or PSAVE bits of the Mode Register.
In transmit mode this bit is '0'.
Status Register B3: CRCERR - CRC Checksum Error
In receive mode this bit will be updated at the end of a SFP, RHB, RILB or RSID task to reflect the result of the
receive CRC check. '0' indicates that the CRC was received correctly, '1' indicates an error. In transmit mode
this bit will be '0'.
Note that this bit should be ignored when an 'Intermediate' block (which does not have an integral CRC) is
received.
The bit is cleared to '0' by a RESET task, or by changing the TXRXN or PSAVE bits of the Mode Register.
Status Register B2: SRDY - 'S' Symbol Ready
In receive mode, this bit is set to '1' whenever an 'S' symbol has been received. The µC may then read the
value of the symbol from the SVAL field of the Status Register. In transmit mode, this bit is set to '1' whenever
an 'S' symbol has been transmitted.
The bit is cleared to '0' immediately after a read of the Status Register, by a RESET task or by changing the
TXRXN or PSAVE bits of the Mode Register.
Status Register B1, B0: SVAL - Received 'S' Symbol Value
In receive mode, these two bits reflect the value of the latest received 'S' symbol. In transmit mode, these two
bits will be '0'.
1.5.5.6 Data Quality Register
© 1996 Consumer Microcircuits Limited
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D/929A/4