CMX994 Datasheet, PDF (33/61 Pages) CML Microcircuits – Local Oscillator

Direct Conversion Receivers
CMX994/CMX994A/CMX994E
7.9
7.9.1
PLL M Divider Register
PLL M Divider: $22 - $20 – 8-bit write only
These registers set the M divider value for the PLL (Feedback Divider). The divider is updated synchronously
when register $22 is written so registers $20 and $21 should be written before $22. Note: the order of writing
$20 and $21 is not important. Bits 7 and 5 also control the PLL and charge-pump blocks and these control bits
are active immediately on any occasion that $22 is written. (Note: To enable the PLL, b2 of the General
Control Register ($11) must also be used; see section 7.2 See also section 6.3.2.
7
6
5
E LD_PLL CP
$22
43
00
$21
21
0
765
4
3
2
0 M17 M16 M15 M14 M13 M12 M11 M10
10
M9 M8
$20
7
6
5
4
3
2
1
0
M7
M6
M5
M4
M3
M2
M1
M0
M17- Phase Locked Loop M divider value
M0
CP $22, b5 = ’1’ enables the charge pump, $22 b5 = ’0’ puts the charge pump into high impedance mode
LD_PLL Only write ‘0’ to b6 of $22 (when read via $D2, this shows the integer N PLL lock status)
E
$22, b7 = ’1’ enables the PLL; b7 = ’0’ disables the PLL –This bit enables the PLL and is ANDed with
General Control Register ($11) b2 – section 7.2 See also section 6.3.2
7.9.2
PLL M Divider: $D2-$D0 - 8-bit read only
These registers read the respective values in registers $20, $21 and $22 ($D0 reads back $20 and $D1 reads
back $21 etc.); see section 7.9.1 for details of bit functions.
Note: $D2 b6 indicates the Synth lock detect status.
 2015 CML Microsystems Plc
Page 33 of 70
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