CMX994 Datasheet, PDF (28/61 Pages) CML Microcircuits – Local Oscillator

Direct Conversion Receivers
CMX994/CMX994A/CMX994E
7.4
7.4.1
Rx Offset Register
Rx Offset: $13 – 8-bit write only
Note: Increased correction range is available in the CMX994A/CMX994E using register $17; see section 7.8.
The bits in registers $13 and $17 control the same hardware functions with the most recent write to $17 or
$13 being applicable at any given time; if $13 is written then QDC5, QDC4, IDC5 and IDC4 in $17 are
automatically set to ‘0’. All bits of registers $13 and $17 are cleared to ‘0’ by a General Reset command.
7
6
5
4
3
2
1
0
QDC3
QDC2
QDC1
QDC0
IDC3
IDC2
IDC1
IDC0
b7-0 I/Q DC offset correction; see section 6.2.1 for further details. The step size can be doubled using the
Rx Control Register ($12), b2; see section 7.3.1.
The values in the table below are the effects of the offset at the maximum VGA gain (minimum
attenuation) setting. They are proportionately lower for lower gain settings (as set by the Rx Gain
Register (b2 – b0). The aim of this Rx Offset Register is to allow output offsets to be reduced
sufficiently (typically <25mV) to avoid any significant reduction in the dynamic range of any
subsequent ADC. It is expected that demodulation software in the baseband processor would be
required to correct for the remaining offset as part of the demodulation process.
See also section 8.1.2.
b3
b2
b1
b0 I Channel at maximum gain
b7
b6
b5
b4 Q Channel at maximum gain
1
1
1
1
-175mV
1
1
1
0
-150mV
1
1
0
1
-125mV
1
1
0
0
-100mV
1
0
1
1
-75mV
1
0
1
0
-50mV
1
0
0
1
-25mV
1
0
0
0
No correction
0
1
1
1
+175mV
0
1
1
0
+150mV
0
1
0
1
+125mV
0
1
0
0
+100mV
0
0
1
1
+75mV
0
0
1
0
+50mV
0
0
0
1
+25mV
0
0
0
0
No correction
7.4.2 Rx Offset: $E3 - 8-bit Read only
This read-only register mirrors the value in register $13; see section 7.4.1 for details of bit functions.
 2015 CML Microsystems Plc
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