CMX994 Datasheet, PDF (18/61 Pages) CML Microcircuits – Local Oscillator

Direct Conversion Receivers
CMX994/CMX994A/CMX994E
6.1
6.1.1
General Operation
Rx/Tx Enable
The CMX994/CMX994A/CMX994E has Tx Enable and Rx Enable pins and the same function can be accessed
via C-BUS using the General Control Register (section 7.2). The logical signals ‘Tx ON’ and ‘Rx ON’ are the
ORed combination of the C-BUS signal and the hardware signals as shown in Table 13. Thus either C-BUS or
hardware enable signals may be used, with the unused mode being set to ‘0’.
Tx (or Rx) Enable Pin
0
1
0
1
C-BUS Tx (or Rx) Enable
0
0
1
1
‘Tx ON’ (or ‘Rx ON’) Result
0
1
1
1
Table 13 Tx (or Rx) Enable Operation
‘Tx ON’ enables the following sections of the device:
 Tx divider (see also Figure 1 and section 7.11.1.
‘Rx ON’ enables the following sections of the device:
 LNA
 Down-converters and I/Q baseband amplifiers
 Rx LO divider
6.2
6.2.1
Receiver Operation
DC Offset Correction
Digitally-controlled dc offset correction is provided which is capable of reducing the offset to 25mV or less for
errors of up to +/-200mV¹ for CMX994 or up to +/-800mV for CMX994A/CMX994E. This represents a
reduction in dynamic range of about 0.1dB for a typical ADC input signal range (2Vp-p) and is therefore
negligible. The required correction must be measured externally as such measurements are application
specific. The correction is applied close to the start of the I/Q baseband chain and therefore maximises
dynamic range in the analogue sections.
The correction is applied in a differential manner so positive and negative corrections are possible; see Figure
12. This allows the dc to be corrected to the nominal dc bias level. The voltage sources are scaled in a binary
fashion so multiple sources can be added to provide the desired correction. The same arrangement applies
independently on both I and Q channels. The CMX994 scheme, shown in Figure 12 / Table 14 is extended in
the CMX994A/CMX994E with four additional sources to increase correction range.
+
Vdc3
+
Vdc2
+
Vdc1
Vdc4
+
Vdc5
+
Vdc6
+
Figure 12 Simplified Schematic of How DC Offset Corrections are Applied
Positive
Terminal
Negative
Terminal
1 _{This can be doubled to 400mV using bit 2 of the Rx Control Register (see section 7.2.1) although this also halves the resolution}
available.
 2015 CML Microsystems Plc
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