CMX994 Datasheet, PDF (23/61 Pages) CML Microcircuits – Local Oscillator

Direct Conversion Receivers
CMX994/CMX994A/CMX994E
In divide-by-4 mode most odd divisions will produce a spur although at low frequencies (circa 100MHz)
operation is spur-free. At circa 300 MHz and above some even divisions are also problematic (in divide-by-4
mode).
It is recommended that for safe operation of the CMX994/CMX994A/CMX994E PLL, receiver LO divide-by-2 or
divide-by-6 modes, with even division ratios, should be used.
When using the CMX994/CMX994A/CMX994E PLL, spurious can also be observed in the output from the
TXLO pin. In this case the spurs are at small offsets from the wanted signal – the offset is linked to the PLL
comparison frequency. The level of these spurs is typically at a very low (< -80 dBc) and less problematic than
in the receiver.
6.3.2
PLL Enable
The PLL block can be enabled from the General Control Register $11, b2 (section 7.2.1) and the PLL M Divider
Register $22, b7 (section 7.9.1). An AND function is performed on these two bits (see table below).
General Control
Register $11, b2
0
0
1
1
PLL M Divider
Register $22, b7
0
1
0
1
PLL Enable
No
No
No
Yes
With the PLL disabled an external local oscillator may be supplied to the CMX994/CMX994A/CMX994E.
 2015 CML Microsystems Plc
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