CS4222_02 Datasheet, PDF (9/29 Pages) Cirrus Logic – 20-Bit Stereo Audio Codec with Volume Control

CS4222
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
RST Low Time
MCLK Frequency
MCLK Pulse Width High
Parameters
MCLK Pulse Width Low
Input Sample Rate
SCLK Frequency
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDIN valid to SCLK rising setup time
SCLK rising to SDIN hold time
SCLK falling to SDOUT valid
Symbol
MCLK = 512 Fs
MCLK = 384 Fs
MCLK = 256 Fs
MCLK = 512 Fs
MCLK = 384 Fs
MCLK = 256 Fs
Fs
(DSCK = 0)
(DSCK = 0)
(DSCK = 0)
(DSCK = 0)
(DSCK = 0)
t_sckh
t_sckl
t_lrckd
t_lrcks
t_ds
t_dh
t_dpd
Min
10
1.014
10
21
31
10
21
31
4
-
40
40
20
40
25
25
-
Max
-
25.6
-
-
-
-
-
-
50
128xFs
-
-
-
-
-
-
----------1----------- + 20
(384) Fs
Units
ms
MHz
ns
ns
kHz
Hz
ns
ns
ns
ns
ns
ns
s
LRCK
SCLK*
SDIN
SDOUT
t _lrckd
t _lrcks
t _sckh
t _sckl
t _sckw
t _{lrpd t ds}
t _dh
MSB
t _dpd
MSB-1
*SCLK shown for DSCK = 0, SCLK inverted for DSCK = 1.
Figure 1. Serial Audio Interface Timing
DS236F1
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