CS4222_02 Datasheet, PDF (10/29 Pages) Cirrus Logic – 20-Bit Stereo Audio Codec with Volume Control

CS4222
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE (SPI) (Inputs:
Logic 0 = DGND, Logic 1 = VD)
Parameter
SPI Mode
CCLK Clock Frequency
RST Rising Edge to CS Falling
CCLK Edge to CS Falling
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
Symbol
Min
f_sck
-
t_srs
500
(Note 8)
t_spi
500
t_csh
1.0
t_css
20
t_scl
66
t_sch
66
t_dsu
40
(Note 9)
t_dh
15
(Note 10)
t_r2
-
(Note 10)
t_f2
-
Max
Unit
6
MHz
-
ns
-
ns
-
µs
-
ns
-
ns
-
ns
-
ns
-
ns
100
ns
100
ns
Notes: 8. t_spi only needed before first falling edge of CS after RST rising edge. t_spi = 0 at all other times.
9. Data must be held for sufficient time to bridge the transition time of CCLK.
10. For f_sclk < 1 MHz.
RST
t _srs
CS
CCLK
C D IN
t _spi t _css
t _scl t _sch
t_csh
t _r2
t _f2
t _dsu t _dh
Figure 2. Control Port Timing - SPI Mode
10
DS236F1