CS4222_02 Datasheet, PDF (14/29 Pages) Cirrus Logic – 20-Bit Stereo Audio Codec with Volume Control

CS4222
4. APPLICATIONS
4.1 Overview
The CS4222 has 2 channels of 20-bit analog-to-digital conversion and 2 channels of 20-bit digital-to-analog
conversion. All ADCs and DACs are delta-sigma converters. The DAC outputs on the CS4222 have adjustable
output attenuation implemented in 0.5 dB step resolution. The device also includes digital de-emphasis for 32,
44.1, and 48 kHz.
Digital audio data for the DACs and from the ADCs is communicated over separate serial ports. This allows
concurrent writing to and reading from the device. The CS4222 is a stand-alone device controlled via pins.
Control for the functions available on the CS4222 are communicated over a serial microcontroller interface.
Figure 4 shows the recommended connection diagram for the CS4222.
The device can be operated with or without the control port interface. Additional functions are available when
the control port interface is used as outlined in Table 1.
Table 1. Control Port vs. Stand-Alone Mode
Control Port
Volume control
Adjustable Mute ramp rate
Enable zero crossing detect
Enable/Disable mute on zero input
De-emphasis
Mute DAC outputs
ADC Input Peak Level Detect
16, 18, 20 bit Interface
Individual ADC/DAC power down
Cal on command
High pass enable/disable
Stand-Alone Mode
-
Fixed Mute ramp rate
Disabled
Enabled
De-emphasis
Mute DAC outputs
-
20 bit I²S Interface
Codec power down
Cal on power-up
High pass enabled
4.2 Analog Inputs
4.2.1 Line Level Inputs
AINR-, AINR+, AINL-, and AINL+ are the differential line level input pins (see Figure 4). Figure 5 shows an
AC coupled optional input buffer which combines level shifting with single-ended to differential conversion.
Analog inputs must be DC coupled into the CS4222 with a 2.3 V common mode input voltage. Any DC offset
at the input to the CS4222 will be removed by the internal high-pass filters (see Figure 6 for the differential
input signal description). The ADC outputs in the CS4222 may be muted (set to zero) by writing the ADMR
and ADML bits, and can be independently powered down using the PDAD bit. ADMR, ADML, and PDAD
are all located in the ADC control byte (#1).
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