CS4222_02 Datasheet, PDF(27/29 Page) Cirrus Logic – 20-Bit Stereo Audio Codec with Volume Control

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CS4222_02 Datasheet, PDF (27/29 Pages) Cirrus Logic – 20-Bit Stereo Audio Codec with Volume Control

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CS4222

DSP Port Mode Byte (5)

DEM2

DEM1

DEM0

DSCK

DDO

DDF2

DEM2-0

Selects de-emphasis control source

0 - De-emphasis controlled by pins

1 - 44.1 kHz de-emphasis setting

2 - 48 kHz de-emphasis setting

3 - 32 kHz de-emphasis setting

4 - De-emphasis disabled

5, 6, 7 - Not used

DSCK

Sets the polarity of clocking data for both input and output

0 - Data valid on rising edge of SCLK

1 - Data valid on falling edge of SCLK

DDO

Data output format

0 - I2S compatible

1 - Left justified

DDI2-DDI0

Data input format

0 - I2S compatible

1 - Left justified

2 - Right justified, 20-bit

3 - Right justified, 18-bit

4 - Right justified, 16-bit

5, 6, 7 - Not used

This register defaults to 00h.

DDF1

DDF0

Converter Status Report Byte (Read Only) (6)

ACCR

ACCL

LVR2

LVR1

LVR0

LVL2

LVL0

ACCR-ACCL

Acceptance bit

0 - ATT7-0 has been accepted

1 - New setting waiting for zero crossing

LVL2-0,LVR2-0

Left and Right ADC output level

0 - Normal output levels

1 - -6 dB level

2 - -5 dB level

3 - -4 dB level

4 - -3 dB level

5 - -2 dB level

6 - -1 dB level

7 - Clipping

LVL2-0 and LVR2-0 bits are 'sticky'. They constantly monitor the ADC output for the peak levels and hold the max-

imum output. They are reset to 0 when the DSP Port Mode Byte (5) is read.

This register is read only.

DS236F1

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