CS4222_02 Datasheet, PDF (19/29 Pages) Cirrus Logic – 20-Bit Stereo Audio Codec with Volume Control

CS4222
4.4 Master Clock Generation
The Master Clock, MCLK, is used to operate the digital filters and the delta-sigma modulator. MCLK must be
either 256x, 384x, or 512x the desired Input Sample Rate, Fs. Fs is the frequency at which digital audio samples
for each channel are input to the DAC or output from the ADC and is equal to the LRCK frequency. The MCLK
to LRCK frequency ratio is detected automatically during the initialization sequence by counting the number of
MCLK transitions during a single LRCK period. Internal dividers are then set to generate the proper clocks for
the digital filters, delta-sigma modulators and switched-capacitor filter. Table 3 illustrates the standard audio
sample rates and the required MCLK frequencies. If MCLK stops for 10 µs, the CS4222 will enter a power down
state until the clock returns. The control port registers will maintain their current settings. It is required to have
SCLK and LRCK derived from the master clock.
Table 3. Common Clock Frequencies
Fs
(kHz)
32
44.1
48
256x
8.1920
11.2896
12.2880
MCLK (MHz)
384x
12.2880
16.9344
18.4320
512x
16.3840
22.5792
24.5760
4.4.1 MCLK Timing Constraint
The rising edge of LRCK must be less than 5 ns or greater than 15 ns after the rising edge of MCLK. This
timing constraint can be met by synchronizing the LRCK with either the rising or falling edge of MCLK.
4.5 Serial Audio Data Interface
4.5.1 Serial Audio Interface Signals
The serial interface clock, SCLK, is used for transmitting and receiving audio data. The active edge of SCLK
is chosen by setting the DSCK bit in the DSP Port Mode Byte (#6). The default on power up is that data is
valid on the rising edge for both input and output. SCLK is an input from an external source and at least
20 SCLK's per half period of LRCK are required for proper operation.
The Left/Right clock (LRCK) is used to indicate left and right data and the start of a new sample period. The
frequency of LRCK must be equal to the system sample rate, Fs.
SDIN is the data input pin which drives a pair of DACs. SDOUT is the output data pin from the ADCs.
4.5.2 Serial Audio Interface Formats
The serial audio port supports 5 input and 2 output formats, shown in Figures 9 and 10. These interface
formats are chosen via the DIF0/DIF1 pins. With the CS4222, these formats are chosen through the DSP
Port Mode Byte (#5) with the DDO and DDI2/1/0 bits. The data output format is 20 bits and may be left jus-
tified or I²S compatible depending on the state of the DDO bit. The input data format is set with the DDI bits
to be left or right justified or I²S compatible. In addition, the polarity of the SCLK edge used to clock in/out
data from the CS4222 may be set via the DSCK bit in the DSP Port Mode Byte (#5). The default input and
output format for the CS4222 is I²S compatible.
DS236F1
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