CS4222_02 Datasheet, PDF (23/29 Pages) Cirrus Logic – 20-Bit Stereo Audio Codec with Volume Control

CS4222
4.8 Power-up / Reset / Power Down / Calibration
Upon power up, the user should hold RST = 0 for approximately 10 ms. In this state, the control port is reset to
its default settings and the part remains in the power down mode. At the end of RST, the device performs an
offset calibration which lasts approximately 50 ms after which the device enters normal operation. A calibration
may also be initiated via the CAL bit in the ADC Control Byte (#1). The CALP bit in the ADC Control Byte is a
read only bit indicating the status of the calibration.
Reset/Power Down is achieved by lowering the RST pin causing the part to enter power down. Once RST goes
high, the control port is functional and the desired settings should be loaded.
The CS4222 will also enter power down mode if the master clock source stops for approximately 10 µs or if the
LRCK is not synchronous to the master clock. The control port will retain its current settings.
Additionally, the PDAD (ADC Control Byte #1) and PDDA (DAC Control Byte #2) bits can be used to power down
the ADC’s and DAC’s independently. If both are set to 1, the CS4222 will power down the entire chip. The control
port will retain its current settings.
The CS4222 will mute the analog outputs and enter the power down mode if the supply drops below
approximately 4 volts.
4.9 Power Supply, Layout and Grounding
As with any high resolution converter, the CS4222 requires careful attention to power supply and grounding
arrangements to optimize performance. The Typical Connection Diagram shows the recommended power
arrangement with VA, and VD connected to clean supplies. Decoupling capacitors should be located as close
to the device package as possible. If desired, all supply pins may be connected to the same supply, but the
recommended decoupling capacitors should still be placed on each supply pin. The AGND and DGND pins
should be tied together with solid ground plane fill underneath the converter extending out to the GND side of
the decoupling caps for VA, and VD. This recommended layout can be seen in the CDB4222 evaluation board
and data sheet.
DS236F1
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