CS4222_02 Datasheet, PDF (11/29 Pages) Cirrus Logic – 20-Bit Stereo Audio Codec with Volume Control

CS4222
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE (I²C) (Continued)
Parameter
Symbol
Min
I²C Mode
SCL Clock Frequency
f_scl
-
RST Rising Edge to Start
t_irs
500
Bus Free Time Between Transmissions
t_buf
4.7
Start Condition Hold Time (prior to first clock pulse)
t_hdst
4.0
Clock Low time
t_low
4.7
Clock High Time
t_high
4.0
Setup Time for Repeated Start Condition
t_sust
4.7
SDA Hold Time from SCL Falling
(Note 11)
t_hdd
0
SDA Setup time to SCL Rising
t_sud
250
Rise Time of SCL and SDA
t_r
-
Fall Time SCL and SDA
t_f
-
Setup Time for Stop Condition
t_susp
4.7
Max
Unit
100
kHz
-
ns
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
ns
1
µs
300
ns
-
µs
Notes: 11. Data must be held for sufficient time to bridge the transition time, t_fc, of SCL.
RST
t _irs
S to p
S ta rt
SDA
t _buf
t _hdst
t _high
R e pe ate d
S ta rt
t _rd
t _hdst
S to p
t _fd
t _fc
t _susp
SCL
t
lo w
t
hdd
t _sud t _ack
t _sust
t _rc
Figure 3. Control Port Timing - I²C Mode
DS236F1
11