CS4354 Datasheet, PDF (8/25 Pages) Cirrus Logic – 5 V Stereo DAC with 2 VRMS Ground-centered Output

CS4354
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
Parameters
Symbol
Min
Typ
Max
Units
MCLK Frequency
7.6
-
55.3
MHz
MCLK Duty Cycle
45
-
55
%
Input Sample Rate
All MCLK/LRCK ratios combined Fs
30
-
216
kHz
(Note 12)
(SSM) 256x, 384x, 512x, 768x, 1024x
30
-
54
kHz
(DSM) 128x, 192x, 256x, 384x, 512x
84
-
108
kHz
(QSM) 128x, 192x, 256x
170
-
216
kHz
External SCLK Mode
LRCK Duty Cycle
45
-
55
%
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Duty Cycle
t_sclkl
20
-
-
ns
t_sclkh
20
-
-
ns
45
-
55
%
SCLK rising to LRCK edge delay
LRCK edge to SCLK rising delay
SDIN valid to SCLK rising setup time
SCLK rising to SDIN hold time
Internal SCLK Mode
t_slrd
20
-
t_slrs
20
-
t_sdlrs
20
-
t_sdh
20
-
-
ns
-
ns
-
ns
-
ns
LRCK Duty Cycle
50% – -2-----_-----M--1---C-----L----K--
-
50% + -2-----_-----M--1---C-----L----K--
-
SCLK Period
(Note 13) t_sclkw
S^----1-C^--0---L^-9--K^---
-
-
ns
MCLK falling to LRCK edge
LRCK edge to SCLK rising
SDIN valid to SCLK rising setup time
t_mclkf
4^-----^---–--M^-1---0-C^---9--L^----K^--
-
4^-----^----1-M^---0--C^-9----L^----K^--
ns
t_sclkr
-
(Note 14)
-
ns
t_sdlrs
5^----1^---21^----0-^--9---F^----s^{- + 10}
-
-
ns
SCLK rising to SDIN hold time
MCLK / LRCK = 1024, 512, 256, 128
t_sdh
5^----1^---21^----0-^--9---F^----s^{- + 15}
-
MCLK / LRCK = 768, 384, 192
3^----8^---41^----0-^--9---F^----s^{- + 15}
-
-
ns
-
12. Not all sample rates are supported for all clock ratios. See Section 4.2 “Sample Rate Range/Operational
Mode Detect” on page 13 for supported ratios and frequencies. SSM = Single-Speed Mode,
DSM = Double-Speed Mode, QSM = Quad-Speed Mode.
13. SCLK period is defined by the SCLK / LRCK ratio. The SCLK / LRCK ratio may be either 32, 48, or 64.
See Table 5 on page 14.
14. tsclkr = ^{t--s----c--2-l--k---w---} + _2---------1-M--0---C-9----L----K-- + tmclkf
8
DS895A2