CS4354 Datasheet, PDF (15/25 Pages) Cirrus Logic – 5 V Stereo DAC with 2 VRMS Ground-centered Output

De-emphasis selection is disabled in the external SCLK mode.
CS4354
Gain
dB
0dB
T1=50 µs
-10dB
T2 = 15 µs
F1
3.183 kHz
F2 Frequency
10.61 kHz
Figure 7. De-Emphasis Curve, Fs = 44.1 kHz
Note: De-emphasis is only available in Single-Speed Mode.
4.5 Internal High-Pass Filter
The CS4354 includes an internal digital high-pass filter. This filter prevents a constant digital offset from cre-
ating a DC voltage on the analog output pins. The filter’s corner frequency is well below the audio band; see
“Switching Specifications - Serial Audio Interface” on page 8 for filter specifications.
4.6 Digital Interface Format
The device accepts audio samples in the industry standard I²S format only.
For an illustration of the required relationship between the LRCK, SCLK and SDIN, see Figure 6 on page
14. SDIN is valid on the rising edge of SCLK. For more information about serial audio formats, refer to Cirrus
Logic Application Note AN282: The 2-Channel Serial Audio Interface: A Tutorial, available at http://www.cir-
rus.com.
4.7 Internal Power-On Reset
The CS4354 features an internal power-on reset (POR) circuit. This circuit monitors the VA supply and au-
tomatically asserts or releases an internal reset of the DAC’s digital circuitry when the supply reaches de-
fined thresholds (see “Internal Power-On Reset Threshold Voltages” on page 10). No external clocks are
required for the POR circuit to function.
VA
GND
Power-On Reset
Circuit
reset
(internal)
Figure 8. Internal Power-On Reset Circuit
When power is first applied, the POR circuit monitors the VA supply voltage to determine when it reaches
a defined threshold, V_on1. At this time, the POR circuit asserts the internal reset low, resetting all of the
DS895A2
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