CS4354 Datasheet, PDF (24/25 Pages) Cirrus Logic – 5 V Stereo DAC with 2 VRMS Ground-centered Output

9. REVISION HISTORY
CS4354
Release
A1 (Sept ‘09)
A2 (July ‘10)
Changes
– Initial release.
– Updated THD+N specification in DAC Analog Characteristics.
– Updated dynamic range specification in DAC Analog Characteristics.
– Updated idle channel noise/SNR specification in DAC Analog Characteristics.
– Updated front page dynamic range and THD+N performance to match updated specifications.
– Updated frequency response specification description in Combined Digital and On-Chip Analog Filter
Characteristics so that frequency response limits are measured relative to 1 kHz.
– Updated Power On Reset threshold values in Internal Power-On Reset Threshold Voltages.
– Removed typical specification for LRCK and SCLK in Switching Specifications - Serial Audio Interface.
– Updated power supply current specifications in DC Electrical Characteristics.
– Updated pin voltage specification in DC Electrical Characteristics.
– Corrected MCLK frequency in Table 4 from 33.8680 MHz to 33.8688 MHz.
– Updated test condition bandwidth in DAC Analog Characteristics from 10 Hz - 20kHz to 20 Hz - 20kHz
– Removed MCLK = 1152x LRCK mode support (per Rev B0 silicon). Updated specifications (LRCK min and
corresponding MCLK min) in Switching Specifications - Serial Audio Interface, and applications information
in Table 4 and Table 5.
– Added (Note 16) to DC Electrical Characteristics.
– Updated FILT+ description in Initialization.
– Updated interchannel isolation specification in DAC Analog Characteristics.
– Updated Table 3 to match specifications in Switching Specifications - Serial Audio Interface.
– Removed High Pass Filter Characteristics section; appended updated specifications to Combined Digital
and On-Chip Analog Filter Characteristics.
– Updated passband and stopband specifications in Combined Digital and On-Chip Analog Filter
Characteristics to reflect Rev B0 silicon.
– Updated title and plots in Combined Digital and On-chip Analog Filter Response Plots to reflect Rev B0
silicon.
– Updated typical output offset in DAC Analog Characteristics.
– Updated timing diagram Figure 2 to reflect internal SCLK generation as shown in Figure 3.
– Updated Typical Connection Diagram; VL capacitor now recommended by default.
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DS895A2