CS4354 Datasheet, PDF (18/25 Pages) Cirrus Logic – 5 V Stereo DAC with 2 VRMS Ground-centered Output

4.9 Recommended Power-Up and Power-Down Sequences
CS4354
4.9.1
Power-Up Sequence
Follow the power-up sequence below:
1. Apply power.
2. After the power supplies are stable, provide the correct MCLK, LRCK, and SCLK (only in External
Serial Clock Mode) signals to progress from the ‘Power-Down State’ in the power-up sequence seen
in Figure 9. Please refer to Section 4.4 on page 14 for common clock frequencies in the External
Serial Clock Mode, and supported modes in the Internal Serial Clock Mode. The sequence will
complete and audio will be output from the AOUTx pins within 50 ms after valid clocks are applied.
4.9.2
Power-Down Sequence
Follow the power-down sequence below:
1. For minimal pops, set the input digital data (SDIN) to zero for at least 8192 consecutive samples.
2. Remove the MCLK signal without applying any glitched pulses to the MCLK pin.
3. Remove the power supply voltages.
Note: A glitched pulse is any pulse that is shorter than the period defined by the minimum/maximum
MCLK signal duty cycle specification and the nominal frequency of the input MCLK signal. A transient may
occur on the analog outputs if the MCLK signal duty cycle specification is violated when the MCLK signal
is removed during normal operation; see “Switching Specifications - Serial Audio Interface” on page 8.
4.10 Grounding and Power Supply Arrangements
As with any high-resolution converter, the CS4354 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. The “Typical Connection Diagram” on page 12
shows the recommended power arrangements with VA and VL connected to clean supplies. It is strongly
recommended that a single ground plane be used with the GND pins connected to the common plane; this
is important because both pin 6 and pin 10 provide analog ground reference to the CS4354. Should it be
necessary to split the ground planes, the CS4354 should be placed entirely in the analog plane. In this con-
figuration, it is critical that the digital and analog ground planes be tied together with a low-impedance con-
nection, ideally a strip of copper on the printed circuit board, at a single point near the CS4354.
All signals, especially clocks, should be kept away from the FILT+ pin in order to avoid unwanted coupling
into the DAC.
4.10.1 Capacitor Placement
Decoupling capacitors should be placed as close to the device as possible, with the low-value ceramic
capacitor being the closest. To further minimize impedance, these capacitors should be located on the
same PCB layer as the device. See DC Electrical Characteristics for the voltage present across pin pairs.
This is useful for choosing appropriate capacitor voltage ratings and orientation if electrolytic capacitors
are used.
The CDB4354 evaluation board demonstrates the optimum layout and power supply arrangements.
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DS895A2