CS4354 Datasheet, PDF (13/25 Pages) Cirrus Logic – 5 V Stereo DAC with 2 VRMS Ground-centered Output

4. APPLICATIONS
CS4354
4.1 Ground-Centered Line Outputs
An on-chip charge pump creates a negative supply which allows the full-scale output swing to be centered
around ground. This eliminates the need for large DC-blocking capacitors which create audible pops at pow-
er-on and provides improved low frequency response. See the DAC Analog Characteristics table for the
complete specifications of the full-scale output voltage. It should be noted that external output impedance
between the AOUTx pin and the load will lower the voltage delivered to the load.
4.2 Sample Rate Range/Operational Mode Detect
The CS4354 operates in one of three operational modes. The device will auto-detect the correct mode when
the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges illustrated in
Table 3. Sample rates outside the specified range for each mode are not supported. In addition to a valid
LRCK frequency, a valid serial clock (SCLK) and master clock (MCLK) must also be applied to the device
for speed mode auto-detection; see Figure 9.
Input Sample Rate (Fs)
30 kHz - 54 kHz
84 kHz - 108 kHz
170 kHz - 216 kHz
Mode
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Table 3. CS4354 Operational Mode Auto-Detect
4.3 System Clocking
The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks.
The left/right clock, defined also as the input sample rate (Fs), must be synchronously derived from the
MCLK signal according to specified ratios. The specified ratios of MCLK to LRCK, along with several stan-
dard audio sample rates and the required MCLK frequency, are illustrated in Table 4 on page 13.
Refer to Section 4.6 for the required SCLK timing associated with the selected Digital Interface Format and
to “Switching Specifications - Serial Audio Interface” on page 8 for the maximum allowed clock frequencies.
LRCK
(kHz)
32
44.1
48
88.2
96
176.4
192
Mode
128x
-
-
-
11.2896
12.2880
22.5792
24.5760
192x
-
-
-
16.9344
18.4320
33.8688
36.8640
QSM
256x
8.1920
11.2896
12.2880
22.5792
24.5760
45.1584
49.1520
MCLK (MHz)
384x
512x
12.2880 16.3840
16.9344 22.5792
18.4320 24.5760
33.8688 45.1584
36.8640 49.1520
-
-
-
-
DSM
Table 4. Common MCLK and LRCK Frequencies
768x
1024x
24.5760
32.7680
33.8688
45.1580
36.8640
49.1520
-
-
-
-
-
-
-
-
SSM
DS895A2
13