CS2300-CP Datasheet, PDF (8/32 Pages) Cirrus Logic – Fractional-N Clock Multiplier with Internal LCO

CS2300-CP
CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT
Inputs: Logic 0 = GND; Logic 1 = VD; C_L = 20 pF.
Parameter
Symbol
Min
Max
SCL Clock Frequency
f_scl
-
Bus Free-Time Between Transmissions
t_buf
4.7
Start Condition Hold Time (prior to first clock pulse)
t_hdst
4.0
Clock Low Time
t_low
4.7
Clock High Time
t_high
4.0
Setup Time for Repeated Start Condition
t_sust
4.7
SDA Hold Time from SCL Falling
(Note 9)
t_hdd
0
SDA Setup Time to SCL Rising
t_sud
250
Rise Time of SCL and SDA
t_r
-
Fall Time SCL and SDA
t_f
-
Setup Time for Stop Condition
t_susp
4.7
Acknowledge Delay from SCL Falling
t_ack
300
Delay from Supply Voltage Stable to Control Port Ready
t_dpor
100
100
-
-
-
-
-
-
-
1
300
-
1000
-
Unit
kHz
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
µs
Notes: 9. Data must be held for sufficient time to bridge the transition time, t_f, of SCL.
VD
SDA
SCL
t_dpor
Repeated
Start
t _buf
t _hdst
t _high
t _hdst
tf
Stop
Start
t _low
t _hdd
t _sud
t _sust
tr
Stop
t _susp
Figure 2. Control Port Timing - I²C Format
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DS843PP1