CS2300-CP Datasheet, PDF (2/32 Pages) Cirrus Logic – Fractional-N Clock Multiplier with Internal LCO

CS2300-CP
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................................. 4
2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5
3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6
RECOMMENDED OPERATING CONDITIONS .................................................................................... 6
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6
DC ELECTRICAL CHARACTERISTICS ................................................................................................ 6
AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7
CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT ................................................... 8
CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT ................................................. 9
4. ARCHITECTURE OVERVIEW ............................................................................................................. 10
4.1 Delta-Sigma Fractional-N Frequency Synthesizer ......................................................................... 10
4.2 Hybrid Analog-Digital Phase Locked Loop .................................................................................... 10
5. APPLICATIONS ................................................................................................................................... 12
5.1 Timing Reference Clock ................................................................................................................. 12
5.2 Frequency Reference Clock Input, CLK_IN ................................................................................... 12
5.2.1 CLK_IN Frequency Detector ................................................................................................. 12
5.2.2 CLK_IN Skipping Mode ......................................................................................................... 13
5.2.3 Adjusting the Minimum Loop Bandwidth for CLK_IN ............................................................ 14
5.3 Output to Input Frequency Ratio Configuration ............................................................................. 15
5.3.1 User Defined Ratio (RUD) ..................................................................................................... 15
5.3.2 Manual Ratio Modifier (R-Mod) ............................................................................................. 16
5.3.3 Automatic Ratio Modifier (Auto R-Mod) ................................................................................. 16
5.3.4 Effective Ratio (REFF) .......................................................................................................... 17
5.3.5 Ratio Configuration Summary ............................................................................................... 18
5.4 PLL Clock Output ........................................................................................................................... 19
5.5 Auxiliary Output .............................................................................................................................. 19
5.6 Clock Output Stability Considerations ............................................................................................ 20
5.6.1 Output Switching ................................................................................................................... 20
5.6.2 PLL Unlock Conditions .......................................................................................................... 20
6. SPI / I²C CONTROL PORT ................................................................................................................... 21
6.1 SPI Control ..................................................................................................................................... 21
6.2 I²C Control ...................................................................................................................................... 21
6.3 Memory Address Pointer ............................................................................................................... 23
6.3.1 Map Auto Increment .............................................................................................................. 23
7. REGISTER QUICK REFERENCE ........................................................................................................ 23
8. REGISTER DESCRIPTIONS ................................................................................................................ 24
8.1 Device I.D. and Revision (Address 01h) ....................................................................................... 24
8.1.1 Device Identification (Device[4:0]) - Read Only ..................................................................... 24
8.1.2 Device Revision (Revision[2:0]) - Read Only ........................................................................ 24
8.2 Device Control (Address 02h) ........................................................................................................ 24
8.2.1 Unlock Indicator (Unlock) - Read Only .................................................................................. 24
8.2.2 PLL Input Sample Rate Indicator (FsDet[1:0]) - Read Only .................................................. 24
8.2.3 Auto R-Modifier Enable (AutoRMod) ..................................................................................... 25
8.2.4 Auxiliary Output Disable (AuxOutDis) ................................................................................... 25
8.2.5 PLL Clock Output Disable (ClkOutDis) .................................................................................. 25
8.3 Device Configuration 1 (Address 03h) ........................................................................................... 25
8.3.1 R-Mod Selection (RModSel[2:0]) ........................................................................................... 25
8.3.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) ............................................................. 26
8.3.3 Enable Device Configuration Registers 1 (EnDevCfg1) ........................................................ 26
8.4 Global Configuration (Address 05h) ............................................................................................... 26
8.4.1 Device Configuration Freeze (Freeze) ................................................................................ 26
8.4.2 Enable Device Configuration Registers 2 (EnDevCfg2) ....................................................... 26
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DS843PP1