CS2300-CP Datasheet, PDF (12/32 Pages) Cirrus Logic – Fractional-N Clock Multiplier with Internal LCO

5. APPLICATIONS
CS2300-CP
5.1 Timing Reference Clock
The internal LC oscillator is used to generate the internal timing reference clock (see section 4 “Architecture
Overview” on page 10 for information on how this internal clock is used by the CS2300). A single 0.1 µF cap
must be connected between the FILTP and FILTN pins and the FILTN pin must be connected to ground as
shown in Figure 6.
FILTN
FILTP
C
Figure 6. External Component Requirements for LCO
5.2 Frequency Reference Clock Input, CLK_IN
The frequency reference clock input (CLK_IN) is used by the Digital PLL and Fractional-N Logic block to
dynamically generate a fractional-N value for the Frequency Synthesizer (see “Hybrid Analog-Digital PLL”
on page 11). The Digital PLL first compares the CLK_IN frequency to the PLL output. The Fractional-N logic
block then translates the desired ratio based off of CLK_IN to one based off of the internal LCO. This allows
the low-jitter internal LCO to be used as the clock which the Frequency Synthesizer multiplies while main-
taining synchronicity with the frequency reference clock through the Digital PLL. The allowable frequency
range for CLK_IN is found in the “AC Electrical Characteristics” on page 7.
5.2.1
CLK_IN Frequency Detector
The CLK_IN frequency range detector determines and indicates the ratio between the frequency of the
internal LCO and the CLK_IN input signal.
The result of the ratio measurement is available in the read-only FsDet[1:0] bits and is also used by the
device to determine the Auto R-Mod value.
FsDetect[1:0]
00
01
10
11
f_LCO / f_{CLK_IN} Ratio
> 224
96 - 224
< 96
Reserved
Table 1. PLL Input Clock Range Indicator
Because f_LCO is known, FsDet[1:0] can then be interpreted as a range for f_{CLK_IN}. This feature is partic-
ularly useful when used in conjunction with the Auto R-Mod feature (see section 5.3.3 on page 16).
Referenced Control
Register Location
FsDet[1:0]..............................“PLL Input Sample Rate Indicator (FsDet[1:0]) - Read Only” section on page 24
12
DS843PP1