CS2300-CP Datasheet, PDF (20/32 Pages) Cirrus Logic – Fractional-N Clock Multiplier with Internal LCO

5.6 Clock Output Stability Considerations
CS2300-CP
5.6.1
Output Switching
CS2300 is designed such that re-configuration of the clock routing functions do not result in a partial clock
period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling or disabling an
output, and the automatic disabling of the output(s) during unlock will not cause a runt or partial clock pe-
riod.
The following exceptions/limitations exist:
• Enabling/disabling AUX_OUT when AuxOutSrc = 11 (unlock indicator).
• Switching AuxOutSrc[1:0] to or from 01 (PLL clock input) and to or from 11 (unlock indicator)
(Transitions between AuxOutSrc[1:0] = [00,10] will not produce a glitch).
• Changing the ClkOutUnl bit while the PLL is in operation.
When any of these exceptions occur, a partial clock period on the output may result.
5.6.2
PLL Unlock Conditions
Certain changes to the clock inputs and registers can cause the PLL to lose lock which will affect the pres-
ence the clock signal on CLK_OUT. The following outlines which conditions cause the PLL to go un-
locked:
• Changes made to the registers which affect the Fraction-N value that is used by the Frequency Syn-
thesizer. This includes all the bits shown in Figure 12 on page 18.
• Any discontinuities on the Timing Reference Clock, REF_CLK.
• Discontinuities on the Frequency Reference Clock, CLK_IN, except when the Clock Skipping feature
is enabled and the requirements of Clock Skipping are satisfied (see “CLK_IN Skipping Mode” on
page 13).
• Gradual changes in CLK_IN frequency greater than ±30% from the starting frequency.
• Step changes in CLK_IN frequency.
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