CS2300-CP Datasheet, PDF (19/32 Pages) Cirrus Logic – Fractional-N Clock Multiplier with Internal LCO

CS2300-CP
5.4 PLL Clock Output
The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer.
The driver can be set to high-impedance with the ClkOutDis bit.
The output from the PLL automatically drives a static low condition while the PLL is un-locked (when the
clock may be unreliable). This feature can be disabled by setting the ClkOutUnl bit, however the state
CLK_OUT may then be unreliable during an unlock condition.
ClkOutUnl
PLL Locked/Unlocked
0
0
2:1 Mux
1
0
2:1 Mux
ClkOutDis
PLL Clock Output
PLLClkOut
PLL Clock Output Pin
(CLK_OUT)
PLL Output
1
Figure 13. PLL Clock Output Options
Referenced Control
Register Location
ClkOutUnl..............................“Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 28
ClkOutDis ..............................“PLL Clock Output Disable (ClkOutDis)” on page 25
5.5 Auxiliary Output
The auxiliary output pin (AUX_OUT) can be mapped, as shown in Figure 14, to one of three signals: input
clock (CLK_IN), additional PLL clock output (CLK_OUT), or a PLL lock indicator (Lock). The mux is con-
trolled via the AuxOutSrc[1:0] bits. If AUX_OUT is set to Lock, the AuxLockCfg bit is then used to control
the output driver type and polarity of the LOCK signal (see section 8.6.2 on page 27). If AUX_OUT is set to
CLK_OUT the phase of the PLL Clock Output signal on AUX_OUT may differ from the CLK_OUT pin. The
driver for the pin can be set to high-impedance using the AuxOutDis bit.
AuxOutSrc[1:0]
Frequency Reference Clock
(CLK_IN)
PLL Clock Output
(PLLClkOut)
PLL Lock/Unlock Indication
(Lock)
3:1 Mux
AuxOutDis
AuxLockCfg
Auxiliary Output Pin
(AUX_OUT)
Figure 14. Auxiliary Output Selection
Referenced Control
Register Location
AuxOutSrc[1:0]......................“Auxiliary Output Source Selection (AuxOutSrc[1:0])” on page 26
AuxOutDis .............................“Auxiliary Output Disable (AuxOutDis)” on page 25
AuxLockCfg...........................“AUX PLL Lock Output Configuration (AuxLockCfg)” section on page 27
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