CS2300-CP Datasheet, PDF (26/32 Pages) Cirrus Logic – Fractional-N Clock Multiplier with Internal LCO

8.3.2
CS2300-CP
Auxiliary Output Source Selection (AuxOutSrc[1:0])
Selects the source of the AUX_OUT signal.
AuxOutSrc[1:0]
00
01
10
11
Application:
Auxiliary Output Source
Reserved.
CLK_IN.
CLK_OUT.
PLL Lock Status Indicator.
“Auxiliary Output” on page 19
Note: When set to 11, AuxLckCfg sets the polarity and driver type (“AUX PLL Lock Output Configura-
tion (AuxLockCfg)” on page 27).
8.3.3
Enable Device Configuration Registers 1 (EnDevCfg1)
This bit, in conjunction with EnDevCfg2 and EnDevCfg3, enables control port mode. All three bits must
be set to 1 during initialization.
EnDevCfg1
0
1
Application:
Register State
Disabled.
Enabled.
“SPI / I²C Control Port” on page 21
Note: EnDevCfg2 and EnDevCfg3 must also be set to enable control port mode (“SPI / I²C Control Port”
on page 21).
8.4 Global Configuration (Address 05h)
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Freeze
2
Reserved
1
Reserved
0
EnDevCfg2
8.4.1
Device Configuration Freeze (Freeze)
Setting this bit allows writes to the Device Control and Device Configuration registers (address 02h - 04h)
but keeps them from taking effect until this bit is cleared.
FREEZE
0
1
Device Control and Configuration Registers
Register changes take effect immediately.
Modifications may be made to Device Control and Device Configuration registers (registers 02h-04h) without
the changes taking effect until after the FREEZE bit is cleared.
8.4.2
Enable Device Configuration Registers 2 (EnDevCfg2)
This bit, in conjunction with EnDevCfg1 and EnDevCfg3, enables control port mode. All three bits must
be set to 1 during initialization.
EnDevCfg2
0
1
Application:
Register State
Disabled.
Enabled.
“SPI / I²C Control Port” on page 21
Note: EnDevCfg1 and EnDevCfg3 must also be set to enable control port mode (“SPI / I²C Control Port”
on page 21).
26
DS843PP1