WM0011 Datasheet, PDF (70/233 Pages) Cirrus Logic – General Purpose Low-Power Audio DSP

WM0011
Production Data
Address = 0xF000_0030
CCM_WKUP_CTRL
CHIP WAKEUP CONTROL REGISTER
Default value = 0x0001_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
3
2
0
FIELD
NAME
WAIT_HIFI_SLP_ENA
WKUP_RST_ENA
STATIC_VECT_SEL
S/W
ACCESS
RW
RW
RW
RESET
VALUE
0x0
0x0
0x0
FIELD
DESCRIPTION
HiFi EP^TM Sleep WAITI control
0 = Do not wait for HiFi WAITI to complete before entering Sleep mode
1 = Wait for HiFi WAITI to complete before entering Sleep mode
Selects whether a Wake-Up (exit from Sleep) triggers a Warm Reset
0 = Wake-Up does not trigger a Warm Reset
1 = Wake-Up triggers a Warm Reset
Selects the DSP core boot vector following a Wake-Up transition.
Only valid when WKUP_RST_ENA=1.
0 = Boot to the primary static vector
1 = Boot to the alternate static vector
Table 25 CCM_WKUP_CTRL Register
CCM_DB_STBY – STANDBY DE-BOUNCE CONTROL REGISTER
The CCM_DB_STBY register configures the de-bounce circuit for the ¯S¯T¯A¯N¯¯D¯B¯Y¯ input pin. The de-
bounced ¯S¯T¯A¯N¯¯D¯B¯Y¯ is an input to the IRQC module, and also one of the DSP core interrupt inputs.
See “Interrupts” for details of the DSP core interrupts.
Address = 0xF000_0044
CCM_DB_STBY
STANDBY DE-BOUNCE CONTROL REGISTER
Default value = 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
FIELD
NAME
S/W
ACCESS
31
STBY_DB_BYP
RW
30:24
Reserved
23:0
STBY_DB_CNT
RW
Table 26 CCM_DB_STBY Register
RESET
VALUE
0x0
0x0
0x00_
0000
FIELD
DESCRIPTION
¯S¯T¯A¯N¯¯D¯B¯Y¯ de-bounce select
0 = De-bounce enabled
1 = De-bounce disabled (bypass)
¯S¯T¯A¯N¯¯D¯B¯Y¯ de-bounce time - sets the number of APBCLK clock cycles
for de-bouncing the ¯S¯T¯A¯N¯¯D¯B¯Y¯ input pin.
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PD, Rev 4.1, August 2013
70