WM0011 Datasheet, PDF (182/233 Pages) Cirrus Logic – General Purpose Low-Power Audio DSP

WM0011
Production Data
DMA CHANNEL CONTROL
The following control attributes are provided for each DMA channel:
 Transfer size – the overall number of bytes to transfer
 Transfer arbitration priority, burst mode/size, chaining mode, watermark threshold, endian swap
mode, other per channel modes
 Base Addresses for both Source and Destination, and a buffer set of these registers
 Address mode for both Source and Destination (eg. fixed addressing for accessing FIFOs,
incrementing addressing for accessing memory)
 Flow Control - can be hardware (ACK) controlled for peripheral modules, or can be software
controlled for memory transfers
MODULE / PATH
Some modules are supported on specific DMA channels only, as noted in Table 131. The required
handshake (ACK) configurations for the associated TX/RX functions must also be observed.
Note that the restriction applies to the particular module, not to the DMA channel.
DMA CHANNEL
HANDSHAKE (ACK) REQUIREMENTS
SPI RX
Channel 4
(No specific requirements)
SPI TX
Channel 5
(No specific requirements)
AIF1 RX
Channel 6
Source Data Phase ACK
DMA_SRC_ACK_CTRL=1
DMA_ADP_ACK_CTRL=0
AIF2 RX
Channel 7
Source Data Phase ACK
DMA_SRC_ACK_CTRL=1
DMA_ADP_ACK_CTRL=0
AIF1 TX
Channel 8
Destination Data Phase ACK
DMA_SRC_ACK_CTRL=0
DMA_ADP_ACK_CTRL=0
AIF2 TX
Channel 9
Destination Data Phase ACK
DMA_SRC_ACK_CTRL=0
DMA_ADP_ACK_CTRL=0
AIF3 RX
Channel 10
Source Data Phase ACK
DMA_SRC_ACK_CTRL=1
DMA_ADP_ACK_CTRL=0
AIF3 TX
Channel 11
Destination Data Phase ACK
DMA_SRC_ACK_CTRL=0
DMA_ADP_ACK_CTRL=0
Note: the Handshake (ACK) configuration is selected using the DMA_SRC_ACK_CTRL and DMA_ADP_ACK_CTRL control fields
in the DMA Control 1 Register (DMA_CTRL1_n)
Table 131 DMA Channel Assignments
The Handshake (ACK) configuration is selected using the DMA_SRC_ACK_CTRL and
DMA_ADP_ACK_CTRL control fields in the DMA Control 1 Register (DMA_CTRL1_n).
Note that the DMA Handshake must also be enabled in the respective path for the applicable
module(s). In the case of the SPI module and AIF modules, refer to the SPI_DMA_CTRL and
AIF_INT_CTRL registers respectively,
w
PD, Rev 4.1, August 2013
182