WM0011 Datasheet, PDF (66/233 Pages) Cirrus Logic – General Purpose Low-Power Audio DSP

WM0011
Production Data
CCM_CLK_ENA – CLOCK ENABLE REGISTER
The CCM_CLK_ENA register contains the enable bits for the clock signals to each peripheral module.
The DSPCLK_SLP_DSBL and AHBCLK_SLP_DSBL bit select whether the respective clock is
enabled in Sleep mode. See “Clocking” for more details of the Clocking architecture.
Address = 0xF000_0024
CCM_CLK_ENA
CLOCK ENABLE REGISTER
Default value = 0x02BA_187F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
31
30
29:26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
FIELD
NAME
DSPCLK_SLP_DSBL
AHBCLK_SLP_DSBL
Reserved
UART_MSTR_CLK_ENA
Reserved
UART_CLK_ENA
TRAX_CLK_ENA
TMR_CLK_ENA
WDT_CLK_ENA
IRQC_CLK_ENA
GPIO_CLK_ENA
FUSE_CLK_ENA
I2C_CLK_ENA
AIF3_MSTR_CLK_ENA
AIF2_MSTR_CLK_ENA
AIF1_MSTR_CLK_ENA
Reserved
S/W
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RESET
VALUE
0x0
0x0
0x0
0x1
0x0
0x1
0x0
0x1
0x1
0x1
0x0
0x1
0x0
0x0
0x0
0x0
0x1
FIELD
DESCRIPTION
DSPCLK control in Sleep mode
0 = DSPCLK enabled in Sleep mode
1 = DSPCLK disabled in Sleep mode
AHBCLK control in Sleep mode
0 = AHBCLK enabled in Sleep mode
1 = AHBCLK disabled in Sleep mode
UART master clock (UART_MSTR_CLK) enable
0 = Disabled
1 = Enabled
Enable APBCLK to UART module
0 = Disabled
1 = Enabled
Enable APBCLK to TRAX module
0 = Disabled
1 = Enabled
Enable APBCLK to TMR modules (TMR1, TMR2 and TMR3)
0 = Disabled
1 = Enabled
Enable APBCLK to WDT module
0 = Disabled
1 = Enabled
Enable APBCLK to IRQC module
0 = Disabled
1 = Enabled
Enable APBCLK to GPIO module
0 = Disabled
1 = Enabled
Enable APBCLK to FUSE module
0 = Disabled
1 = Enabled
Enable APBCLK to I2C module
0 = Disabled
1 = Enabled
AIF3 master clock (AIF3_MSTR_CLK) enable
0 = Disabled
1 = Enabled
AIF3 master clock (AIF3_MSTR_CLK) enable
0 = Disabled
1 = Enabled
AIF3 master clock (AIF3_MSTR_CLK) enable
0 = Disabled
1 = Enabled
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PD, Rev 4.1, August 2013
66