English
Language : 

WM0011 Datasheet, PDF (155/233 Pages) Cirrus Logic – General Purpose Low-Power Audio DSP
WM0011
Production Data
Address = 0xF008_0008
UART_FIFO_CTRL
UART FIFO CONTROL REGISTER
Default value = 0x00
7654321 0
BITS
0
FIELD
NAME
FIFO_ENA
S/W
ACCESS
W
RESET
VALUE
0x0
FIELD
DESCRIPTION
FIFO mode enable
0 = Disabled
1 = Enabled
When FIFO mode is enabled, a 16-word buffer is provided in the UART
TX and RX data paths.
When FIFO mode is disabled, a 1-word buffer is implemented in the
UART TX and RX data paths.
Table 113 UART_FIFO_CTRL Register
UART_INT_STATUS - UART INTERRUPT STATUS REGISTER
The UART_FIFO_CTRL and UART_INT_STATUS registers both exist at the same address; the
applicable description depends on whether the register action is a Read or a Write operation.
The UART_INT_STATUS register is defined in Table 114. Note that this definition is valid for register
Read operations only.
Address = 0xF008_0008
UART_INT_STATUS
UART INTERRUPT STATUS REGISTER
Default value = 0x00
7654321 0
BITS
7:6
5:4
3:1
0
FIELD
NAME
FIFO_ENA_STS
Reserved
INT_STATUS
INT_STS_N
S/W
ACCESS
R
R
R
R
RESET
VALUE
0x0
0x0
0x0
FIELD
DESCRIPTION
UART FIFO Enable status
00 = Disabled
11 = Enabled
All other codes are Reserved
UART Interrupt Status Description
0h = Modem Status Change Interrupt (Priority 4)
1h = TX Buffer Empty Interrupt (Priority 3)
2h = RX Data Available Interrupt (Priority 2a)
3h = RX Line Status Interrupt (Priority 1)
6h = RX Timeout Interrupt (Priority 2b) - see note below
Only valid when INT_STS_N=0.
This field provides an indication of the highest-priority UART Interrupt.
Priority ‘1’ is highest priority.
The RX Timeout Interrupt occurs if received data is not read from the
UART_DAT register within a timeout period (equal to 4 x UART
Character Period).
UART Interrupt Status
0 = UART Interrupt is asserted
1 = UART Interrupt is not asserted
Note that, when a UART Interrupt is asserted (INT_STS_N=0), the
INT_STATUS field provides an indication of the highest priority enabled
and asserted UART Interrupt.
Table 114 UART_INT_STATUS Register
w
PD, Rev 4.1, August 2013
155