WM0011 Datasheet, PDF (43/233 Pages) Cirrus Logic – General Purpose Low-Power Audio DSP

WM0011
CLOCKING
Production Data
The WM0011 requires a clock reference for its internal functions, and to provide clocking for external
interfaces when Master mode is selected on the respective module(s).
The external clock reference is connected via the XTI pin; this may be either a digital logic input, or
may be provided using an external crystal. A two-stage PLL is provided, allowing a high frequency
internal clock to be generated from the XTI clock input reference.
The clocking architecture is illustrated in Figure 16. The CLKIN reference (direct from the XTI pin) can
provide clocking to all modules directly, and is also used as the input clock to the PLL. An alternate
clock (ALTCLK) can also be configured using a GPIO pin as input.
The clock source for most of the WM0011 functions is selected using the CLK_SEL multiplexer; this
provides a glitch-free switchover between the CLKIN, PLLOUT or ALTCLK signals. Note that, if a
Warm Reset is triggered due to the PLL ‘out-of-lock’ condition, then the CLK_SEL multiplexer forces
the selection of CLKIN as the system clock source. This override must be cleared before any other
clock source can be selected.
The clock reference selected by CLK_SEL is processed by configurable dividers to generate the
following system clocks:
 DSPCLK - clock reference for the HiFi2 EP^TM DSP core
 AHBCLK - clock reference for selected peripherals
 APBCLK - clock reference for selected peripherals
The main clocking options are summarised as follows:
 Under initial start-up conditions, CLKIN is selected as the clock source.
 High-speed clocking is possible when the PLL is configured, and PLLOUT is selected as the
clock source.
 The alternative clock source, ALTCLK provides the option of a low-speed clocking configuration;
this could be used for a low-power operating mode, or if CLKIN was unsuitable or unavailable.
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PD, Rev 4.1, August 2013
43