WM0011 Datasheet, PDF (214/233 Pages) Cirrus Logic – General Purpose Low-Power Audio DSP

WM0011
Production Data
accessible by means of memory mapped registers and ports. The back-end interface supports
blocking transactions.
AIF INTERFACE FORMATS
The AIF digital audio interface ports comprise 4 external connections:
 AIFnTXDAT - Data output
 AIFnRX_DAT - Data input
 AIFnLRCLK - Left/Right frame alignment clock
 AIFnBCLK - Bit clock, for data synchronisation
In Master mode, the clock signals BCLK and LRCLK are outputs from the WM0011. In Slave mode,
these signals are inputs.
The AIF data format is highly configurable, using the AIF_DATA_CFG and AIF_CLK_CFG registers
(see Table 173 and Table 174). The AIF modules support I2S, Left-Justified, Right-Justified, DSP
Mode-A, DSP Mode-B formats, and many others. Typical configurations are described and illustrated
below.
In I²S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.
The other bits up to the LSB are then transmitted in order. Depending on the Channel length and
Sample length configuration, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.
Figure 52 I2S Justified Audio Interface
In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK
transition. The other bits up to the LSB are then transmitted in order. Depending on the Channel
length and Sample length configuration, there may be unused BCLK cycles before each LRCLK
transition.
Figure 53 Left Justified Audio Interface
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PD, Rev 4.1, August 2013
214