WM0011 Datasheet, PDF (138/233 Pages) Cirrus Logic – General Purpose Low-Power Audio DSP

WM0011
Production Data
Address = 0xF005_002C
IRQC_FIRQ_MSK
IRQ FAST INTERRUPT MASK REGISTER
Default value = 0xFFFF_FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
5
4
3
2
1
0
FIELD NAME
AIF2_FIRQ_MSK
AIF1_FIRQ_MSK
UART_FIRQ_MSK
SPI_FIRQ_MSK
GPIO_FIRQ_MSK
S/W
ACCESS
RW
RW
RW
RW
RW
RW
RESET
VALUE
0x1
0x1
0x1
0x1
0x1
0x1
FIELD DESCRIPTION
Selects whether AIF2 Interrupt is masked. A masked interrupt will not
trigger the AIF2_FIRQ_STS bit, and is disabled from the
IRQC_FIRQ_VECT logic.
0 = Enabled; 1 = Masked.
Selects whether AIF1 Interrupt is masked. A masked interrupt will not
trigger the AIF1_FIRQ_STS bit, and is disabled from the
IRQC_FIRQ_VECT logic.
0 = Enabled; 1 = Masked.
Selects whether UART Interrupt is masked. A masked interrupt will not
trigger the UART_FIRQ_STS bit, and is disabled from the
IRQC_FIRQ_VECT logic.
0 = Enabled; 1 = Masked.
Selects whether SPI Interrupt is masked. A masked interrupt will not
trigger the SPI_FIRQ_STS bit, and is disabled from the
IRQC_FIRQ_VECT logic.
0 = Enabled; 1 = Masked.
Selects whether GPIO Interrupt is masked. A masked interrupt will not
trigger the GPIO_FIRQ_STS bit, and is disabled from the
IRQC_FIRQ_VECT logic.
0 = Enabled; 1 = Masked.
Reserved - set to 1 only
Table 92 IRQC_FIRQ_MSK Register
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PD, Rev 4.1, August 2013
138