EP7312 Datasheet, PDF (5/64 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM ON CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE

List of Figures
EP7312
High-Performance, Low-Power System on Chip
Figure 1. A Fully-Configured EP7312-Based System ................................................................................................... 12
Figure 2. Legend for Timing Diagrams ......................................................................................................................... 15
Figure 3. SDRAM Load Mode Register Cycle Timing Measurement ............................................................................ 17
Figure 4. SDRAM Burst Read Cycle Timing Measurement .......................................................................................... 18
Figure 5. SDRAM Burst Write Cycle Timing Measurement .......................................................................................... 19
Figure 6. SDRAM Refresh Cycle Timing Measurement ................................................................................................ 20
Figure 7. Static Memory Single Read Cycle Timing Measurement ...............................................................................22
Figure 8. Static Memory Single Write Cycle Timing Measurement ...............................................................................23
Figure 9. Static Memory Burst Read Cycle Timing Measurement ................................................................................ 24
Figure 10. Static Memory Burst Write Cycle Timing Measurement .............................................................................. 25
Figure 11. SSI1 Interface Timing Measurement ........................................................................................................... 26
Figure 12. SSI2 Interface Timing Measurement ........................................................................................................... 27
Figure 13. LCD Controller Timing Measurement .......................................................................................................... 28
Figure 14. JTAG Timing Measurement ......................................................................................................................... 29
Figure 15. 208-Pin LQFP Package Outline Drawing .................................................................................................... 30
Figure 16. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram .......................................................................... 31
Figure 17. 204-Ball TFBGA Package ............................................................................................................................38
Figure 18. 256-Ball PBGA Package .............................................................................................................................. 46
List of Tables
Table 1. Power Management Pin Assignments ..............................................................................................................6
Table 2. Static Memory Interface Pin Assignments ........................................................................................................6
Table 3. SDRAM Interface Pin Assignments ..................................................................................................................7
Table 4. Universal Asynchronous Receiver/Transmitters Pin Assignments ...................................................................7
Table 5. DAI Interface Pin Assignments .........................................................................................................................7
Table 6. CODEC Interface Pin Assignments ..................................................................................................................8
Table 7. SSI2 Interface Pin Assignments .......................................................................................................................8
Table 8. Serial Interface Pin Assignments ......................................................................................................................8
Table 9. LCD Interface Pin Assignments ........................................................................................................................8
Table 10. Keypad Interface Pin Assignments .................................................................................................................9
Table 11. Interrupt Controller Pin Assignments ..............................................................................................................9
Table 12. Real-Time Clock Pin Assignments ..................................................................................................................9
Table 13. PLL and Clocking Pin Assignments ................................................................................................................9
Table 14. DC-to-DC Converter Interface Pin Assignments ...........................................................................................10
Table 15. General Purpose Input/Output Pin Assignments .......................................................................................... 10
Table 16. Hardware Debug Interface Pin Assignments ................................................................................................ 10
Table 17. LED Flasher Pin Assignments ...................................................................................................................... 10
Table 18. DAI/SSI2/CODEC Pin Multiplexing ............................................................................................................... 11
Table 19. Pin Multiplexing .............................................................................................................................................11
Table 20. 208-Pin LQFP Numeric Pin Listing ............................................................................................................... 32
Table 21. 204-Ball TFBGA Ball Listing ......................................................................................................................... 40
Table 22. 256-Ball PBGA Ball Listing ........................................................................................................................... 49
Table 23. JTAG Boundary Scan Signal Ordering .........................................................................................................54
Table 24. Acronyms and Abbreviations ........................................................................................................................ 60
Table 25. Unit of Measurement ..................................................................................................................................... 60
Table 26. Pin Description Conventions ......................................................................................................................... 61
DS508PP5
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