EP7312 Datasheet, PDF (46/64 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM ON CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE

EP7312
High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Ball Location
Name
Strength^†
Reset
State
Type
Description
Y11
SMPCLK
1
Low
O
SSI1 ADC sample clock
Y12
FB[1]
I
PWM feedback input
Y13
COL[6]
1
High
O
Keyboard scanner column drive
Y14
COL[3]
1
High
O
Keyboard scanner column drive
Y15
COL[1]
1
High
O
Keyboard scanner column drive
Y16
D[31]
1
Low
I/O
Data I/O
Y17
D[28]
1
Low
I/O
Data I/O
Y18
D[27]
1
Low
I/O
Data I/O
Y19
A[25]/DRA[2]
2
Low
O
System byte address / SDRAM address
Y20
VDDIO
Pad power
Digital I/O power, 3.3V
*_{“With p/u” means with internal pull-up of 100 KOhms on the pin.}
† _{Strength 1 = 4 ma}
Strength 2 = 12 ma
‡_{Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions.}
256-Ball PBGA Package Characteristics
Figure 18. 256-Ball PBGA Package
Note: 1) For pin locations see Table 22.
2) Dimensions are in millimeters (inches), and controlling dimension is millimeter
3) Before beginning any new EP7312 design, contact Cirrus Logic for the latest package information.
46
©Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS508PP5