EP7312 Datasheet, PDF(20/64 Page) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM ON CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE

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EP7312 Datasheet, PDF (20/64 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM ON CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE

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EP7312

High-Performance, Low-Power System on Chip

SDRAM Refresh Cycle

SDCLK

SDCS

SDRAS

SDCAS

SDATA

ADDR

SDQM

[3:0]

SDMWE

tCSa

tRAa

tCSd

tRAd

tCAa

tCAd

Figure 6. SDRAM Refresh Cycle Timing Measurement

Note:

1. Timings are shown with CAS latency = 2

2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.

Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal

DS508PP5

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