CS4350_07 Datasheet, PDF (4/41 Pages) Cirrus Logic – 192 kHz Stereo DAC with Integrated PLL

CS4350
8.2.2 De-Emphasis Control (DEM[1:0]) Bits 3-2 ........................................................................... 30
8.2.3 Functional Mode (FM[1:0]) Bits 1-0...................................................................................... 30
8.3 Volume Mixing and Inversion Control - Register 03h .................................................................... 30
8.3.1 Channel A Volume = Channel B Volume (VOLB=A) Bit 7 ................................................... 30
8.3.2 Invert Signal Polarity (INVERT_A) Bit 6 ............................................................................... 30
8.3.3 Invert Signal Polarity (INVERT_B) Bit 5 ............................................................................... 31
8.3.4 ATAPI Channel Mixing and Muting (ATAPI[3:0]) Bits 3-0 .................................................... 31
8.4 Mute Control - Register 04h ......................................................................................................... 32
8.4.1 Auto-Mute (AMUTE) Bit 7 .................................................................................................... 32
8.4.2 AMUTEC = BMUTEC (MUTEC A=B) Bit 5 .......................................................................... 32
8.4.3 Channel A Mute (MUTE_A) Bit 4 & Channel B Mute (MUTE_B) Bit 3................................. 32
8.5 Channel A & B Volume Control - Register 05h & 06h ................................................................... 33
8.6 Ramp and Filter Control - Register 07h ......................................................................................... 33
8.6.1 Soft Ramp and Zero Cross Control (SZC[1:0]) Bits 7-6 ....................................................... 33
8.6.2 Soft Volume Ramp-Up after Error (RMP_UP) Bit 5 ............................................................. 34
8.6.3 Soft Ramp-Down before Filter Mode Change (RMP_DN) Bit 4 ........................................... 34
8.6.4 Interpolation Filter Select (FILT_SEL) Bit 2.......................................................................... 34
8.7 Misc. Control - Register 08h .......................................................................................................... 34
8.7.1 Power Down (PDN) Bit 7...................................................................................................... 34
8.7.2 Freeze Controls (FREEZE) Bit 5.......................................................................................... 35
8.7.3 Popguard Enable (POPG_EN) Bit 4 .................................................................................... 35
8.7.4 RMCK control (RMCK_CTRL[1:0]) Bits 3:2 ......................................................................... 35
8.7.5 RMCK Ratio Select (R_SELECT[1:0]) Bits 2:1 .................................................................... 35
9. FILTER PLOTS .................................................................................................................................. 36
10. PARAMETER DEFINITIONS............................................................................................................... 38
11. PACKAGE DIMENSIONS ................................................................................................................... 39
THERMAL CHARACTERISTICS ............................................................................................................... 39
12. ORDERING INFORMATION ............................................................................................................... 40
13. REVISION HISTORY .......................................................................................................................... 40
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DS691F1