CS4350_07 Datasheet, PDF (15/41 Pages) Cirrus Logic – 192 kHz Stereo DAC with Integrated PLL

CS4350
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
Inputs: Logic 0 = GND; Logic 1 = VLC; C_L = 20 pF.
Parameter
CCLK Clock Frequency
RST Rising Edge to CS Falling
CCLK Edge to CS Falling (Note 12)
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time (Note 13)
Rise Time of CCLK and CDIN (Note 14)
Fall Time of CCLK and CDIN (Note 14)
Transition Time from CCLK to CDOUT Valid (Note 15)
Time from CS rising to CDOUT High-Z
Symbol
f_sclk
t_srs
t_spi
t_csh
t_css
t_scl
t_sch
t_dsu
t_dh
t_r2
t_f2
t_scdov
t_cscdo
Min
-
500
500
1.0
20
66
66
40
15
-
-
-
-
Max
6
-
-
-
-
-
-
-
-
100
100
100
100
Unit
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes: 12. t_spi only needed before first falling edge of CS after RST rising edge. t_spi = 0 at all other times.
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For F_SCK < 1 MHz.
15. CDOUT should not be sampled during this time.
RST
t _srs
CS
CCLK
CDIN
CDOUT
t _spi t _css
t _scl t _sch
t _r2
t _f2
t _csh
t _{dsu t dh}
H i-Im p e da n ce
t _scdov
t _scdov
t _cscdo
Figure 9. Control Port Timing - SPI Mode
DS691F1
15