CS4350_07 Datasheet, PDF (27/41 Pages) Cirrus Logic – 192 kHz Stereo DAC with Integrated PLL

6.3.2
CS
CS4350
SPI Read
To read from the device, follow the procedure below while adhering to the values specified in ”Switching
Characteristics - Control Port - SPI Format” on page 15.
1. Bring CS low.
2. The address byte on the CDIN pin must then be 10011111 (R/W = 1).
3. CDOUT pin will then output the data from the register pointed to by the MAP, which is set during the
SPI write operation.
4. If the INCR bit (see Section 6.1) is set to 1, keep CS low and continue providing clocks on CCLK to
read from multiple consecutive registers. Bring CS high when reading is complete.
5. If the INCR bit is set to 0 and further SPI reads from other registers are desired, it is necessary to bring
CS high, and follow the procedure detailed from step 1. If no further reads from other registers are
desired, bring CS high.
CCLK
CDIN
C H IP
ADDRESS
1001111
MAP
DATA
R/W
MSB
LSB
b yte 1
b yte n
C H IP
ADDRESS
1001111 _R/W
CDOUT
High Impedance
MSB
LSB MSB
LSB
MAP = Memory Address Pointer, 8 bits, MSB first
Figure 20. Control Port Timing, SPI Mode
6.4 Memory Address Pointer (MAP)
7
6
5
4
INCR
Reserved
Reserved
Reserved
0
0
0
0
6.4.1
INCR (Auto Map Increment Enable)
Default = ‘0’
0 - Disabled
1 - Enabled
6.4.2 MAP (Memory Address Pointer)
Default = ‘0000’
3
MAP3
0
2
MAP2
0
1
MAP1
0
0
MAP0
0
DS691F1
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