CS4350_07 Datasheet, PDF (13/41 Pages) Cirrus Logic – 192 kHz Stereo DAC with Integrated PLL

CS4350
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
Inputs: Logic 0 = GND; Logic 1 = VLS; C_L = 20 pF.
Parameters
Symbol Min
3.14 V ≤ VA ≤ 5.25 V and 1.35 V ≤ VLS ≤ 5.25 V
RMCK Output Frequency (Note 10)
7.680
RMCK Output Duty Cycle
45
Input Sample Rate
Single-Speed Mode
30
Double-Speed Mode Fs
60
Quad-Speed Mode
120
LRCK Duty Cycle (Non-TDM Mode)
40
SDIN Setup Time Before SCLK Rising Edge
t_ds
1
SDIN Hold Time After SCLK Rising Edge
t_dh
1
4.75 V ≤ VA ≤ 5.25 V and 3.14 V ≤ VLS ≤ 5.25 V
SCLK Frequency
-
SCLK High Time
SCLK Low Time
Non-TDM Mode (refer to Figure 6)
t_sckh
6
t_sckl
6
LRCK Edge to SCLK Rising Edge
SCLK Rising Edge to LRCK Edge
TDM Mode (refer to Figure 7)
t_lcks
11
t_lckd
1
LRCK High Time
t_lrckh
6
SCLK Rising to LRCK Falling Edge
t_fsh
3
LRCK Rising Edge to SCLK Rising Edge
t_fss
1
3.14 V ≤ VA < 4.75 V or 1.35 V ≤ VLS < 3.14 V
SCLK Frequency
-
SCLK High Time
SCLK Low Time
Non-TDM Mode (refer to Figure 6)
t_sckh
11
t_sckl
11
LRCK Edge to SCLK Rising Edge
SCLK Rising Edge to LRCK Edge
TDM Mode (refer to Figure 7)
t_lcks
16
t_lckd
1
LRCK High Time
SCLK Rising to LRCK Falling Edge
LRCK Rising Edge to SCLK Rising Edge
t_lrckh
25
t_fsh
8
t_fss
1
Max
55.3
55
54
108
216
60
-
-
55.3
-
-
-
-
-
-
-
27.7
-
-
-
-
-
-
-
Units
MHz
%
kHz
%
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
Note: 10. RMCK output frequency depends on the input LRCK frequency. See Section 4.1 and Section 4.2 for
more details.
DS691F1
13