CS2100-OTP Datasheet, PDF (3/28 Pages) Cirrus Logic – Fractional-N Clock Multiplier

CS2100-OTP
7.1 High Resolution 12.20 Format ....................................................................................................... 25
7.2 High Multiplication 20.12 Format ................................................................................................... 25
8. PROGRAMMING INFORMATION ........................................................................................................ 26
9. PACKAGE DIMENSIONS .................................................................................................................... 27
THERMAL CHARACTERISTICS ......................................................................................................... 27
10. ORDERING INFORMATION .............................................................................................................. 28
11. REVISION HISTORY .......................................................................................................................... 28
LIST OF FIGURES
Figure 1. Typical Connection Diagram ........................................................................................................ 5
Figure 2. Delta-Sigma Fractional-N Frequency Synthesizer ....................................................................... 8
Figure 3. Hybrid Analog-Digital PLL ............................................................................................................ 9
Figure 4. Internal Timing Reference Clock Divider ................................................................................... 10
Figure 5. External Component Requirements for Crystal Circuit .............................................................. 11
Figure 6. CLK_IN removed for > 223 SysClk cycles ................................................................................. 12
Figure 7. CLK_IN removed for < 223 SysClk cycles but > tCS ................................................................. 12
Figure 8. CLK_IN removed for < tCS ........................................................................................................ 13
Figure 9. Low bandwidth and new clock domain ...................................................................................... 13
Figure 10. High bandwidth with CLK_IN domain re-use ........................................................................... 14
Figure 11. Ratio Feature Summary ........................................................................................................... 17
Figure 12. PLL Clock Output Options ....................................................................................................... 17
Figure 13. Auxiliary Output Selection ........................................................................................................ 18
Figure 14. M2 Mapping Options ................................................................................................................ 19
Figure 15. Parameter Configuration Sets .................................................................................................. 21
LIST OF TABLES
Table 1. Modal and Global Configuration .................................................................................................. 10
Table 2. Ratio Modifier .............................................................................................................................. 15
Table 3. Automatic Ratio Modifier ............................................................................................................. 15
Table 4. Example Audio Oversampling Clock Generation from CLK_IN .................................................. 16
Table 5. Example 12.20 R-Values ............................................................................................................ 25
Table 6. Example 20.12 R-Values ............................................................................................................ 25
DS841PP1
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