CS2100-OTP Datasheet, PDF (20/28 Pages) Cirrus Logic – Fractional-N Clock Multiplier

5.8 Clock Output Stability Considerations
CS2100-OTP
5.8.1
Output Switching
The CS2100-OTP is designed such that re-configuration of the clock routing functions do not result in a
partial clock period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling or
disabling an output, changing the auxiliary output source between REF_CLK and CLK_OUT, and the au-
tomatic disabling of the output(s) during unlock will not cause a runt or partial clock period.
The following exceptions/limitations exist:
• Enabling/disabling AUX_OUT when AuxOutSrc = 11 (unlock indicator).
• Switching AuxOutSrc[1:0] to or from 01 (CLK_IN) and to or from 11 (unlock indicator)
(Transitions between AuxOutSrc[1:0] = [00,10] will not produce a glitch).
When any of these exceptions occur, a partial clock period on the output may result.
5.8.2
PLL Unlock Conditions
Certain changes to the clock inputs and mode pins can cause the PLL to lose lock which will affect the
presence of a clock signal on CLK_OUT. The following outlines which conditions cause the PLL to go un-
locked:
• Any change in the state of the M1 and M0 pins will cause the PLL to temporarily lose lock as the new
setting takes affect.
• Changes made to the state of the M2 when the M2Config[2:0] global parameter is set to 011, 100, 101,
or 110 can cause the PLL to temporarily lose lock as the new setting takes affect.
• Any discontinuities on the Timing Reference Clock, REF_CLK.
• Discontinuities on the Frequency Reference Clock, CLK_IN, except when the Clock Skipping feature
is enabled and the requirements of Clock Skipping are satisfied (see “CLK_IN Skipping Mode” on
page 11).
• Gradual changes in CLK_IN frequency greater than ±30% from the starting frequency.
• Step changes in CLK_IN frequency.
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