CS2100-OTP Datasheet, PDF (14/28 Pages) Cirrus Logic – Fractional-N Clock Multiplier

CS2100-OTP
CLK_OUT signal in order to maintain phase alignment. For these applications, it is advised to experiment
with the loop bandwidth settings and choose the lowest bandwidth setting that does not produce system
timing errors due to wandering between the clocks and data synchronous to the CLK_IN domain and
those synchronous to the PLL_OUT domain.
Wander < 128 Hz
CLK_IN
Jitter
PLL
PLL_OUT
BW = 128 Hz
Jitter > 128 Hz Rejected
Wander < 128 Hz Passed to Output
MCLK
MCLK
LRCK
SCLK
or
Subclocks and data re-used
from previous clock domain.
LRCK
SCLK
SDATA
D0
D1
SDATA
Figure 10. High bandwidth with CLK_IN domain re-use
D0
D1
While acquiring lock, the digital loop bandwidth is automatically set to a large value. Once lock is
achieved, the digital loop bandwidth will settle to the minimum value selected by the ClkIn_BW[2:0] pa-
rameter.
Referenced Control
Parameter Definition
ClkIn_BW[2:0] .......................“Clock Input Bandwidth (ClkIn_BW[2:0])” on page 24
5.4 Output to Input Frequency Ratio Configuration
5.4.1
User Defined Ratio (R_UD)
The User Defined Ratio, R_UD, is a 32-bit un-signed fixed-point number which determines the basis for the
desired input to output clock ratio. Up to four different ratios, Ratio_0-3, can be stored in the CS2100’s one
time programmable memory. Selection between the four ratios is achieved by the M[1:0] mode select
pins. The 32-bit R_UD can be expressed in either a high resolution (12.20) or high multiplication (20.12)
format selectable by the LFRatioCfg global parameter.
The R_UD for high resolution (12.20) format is encoded with 12 MSBs representing the integer binary por-
tion with the remaining 20 LSBs representing the fractional binary portion. The maximum multiplication
factor is approximately 4096 with a resolution of 0.954 PPM in this configuration. See “Calculating the
User Defined Ratio” on page 25 for more information.
The R_UD for high multiplication (20.12) format is encoded with 20 MSBs representing the integer binary
portion with the remaining 12 LSBs representing the fractional binary portion. In this configuration, the
maximum multiplication factor is approximately 1,048,575 with a resolution of 244 PPM. It is recommend-
ed that the 12.20 High-Resolution format be utilized whenever the desired ratio is less than 4096 since
the output frequency accuracy of the PLL is directly proportional to the accuracy of the timing reference
clock and the resolution of the R_UD.
The status of internal dividers, such as the internal timing reference clock divider, are automatically taken
into account. Therefore R_UD is simply the desired ratio of the output to input clock frequencies.
Referenced Control
Parameter Definition
Ratio 0-3................................“Ratio 0 - 3” on page 22
LFRatioCfg ............................“Low-Frequency Ratio Configuration (LFRatioCfg)” on page 23
M[1:0] ....................................“M1 and M0 Mode Pin Functionality” on page 18
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