CS2100-OTP Datasheet, PDF (17/28 Pages) Cirrus Logic – Fractional-N Clock Multiplier

CS2100-OTP
ratio R_EFF, the final calculation used to determine the output to input clock ratio. The effective ratio is then
corrected for the internal dividers. The conceptual diagram in Figure 11 summarizes the features involved
in the calculation of the ratio values used to generate the fractional-N value which controls the Frequency
Synthesizer. The subscript ‘4’ indicates the modal parameters.
Timing Reference Clock
(XTI/REF_CLK)
Effective Ratio REFF
M[1:0] pins
User Defined Ratio RUD
Ratio 0
Ratio 1
Ratio 2
Ratio Format
12.20
20.12
Ratio 3
LFRatioCfg
M2 pin
RModSel[1:0]4
RefClkDiv[1:0]
Ratio
Modifier
Auto
R-Mod
R Correction
AutoRMod4
or M2 pin
FsDet[1:0]
Divide
RefClkDiv[1:0]
SysClk
Digital PLL &
Fractional N Logic
Dynamic Ratio, ‘N’
Frequency
Synthesizer
Frequency Reference Clock
(CLK_IN)
PLL Output
Figure 11. Ratio Feature Summary
Referenced Control
Parameter Definition
Ratio 0-3................................“Ratio 0 - 3” on page 22
M[1:0] pins.............................“M1 and M0 Mode Pin Functionality” on page 18
LFRatioCfg ............................“Low-Frequency Ratio Configuration (LFRatioCfg)” on page 23
RModSel[1:0] ........................“R-Mod Selection (RModSel[1:0])” section on page 21
AutoRMod .............................“Auto R-Modifier Enable (AutoRMod)” on page 22
RefClkDiv[1:0] .......................“Reference Clock Input Divider (RefClkDiv[1:0])” on page 23
5.5 PLL Clock Output
The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer.
The driver can be set to high-impedance with the M2 pin when the M2Config[1:0] global parameter is set to
either 000 or 010. The output from the PLL automatically drives a static low condition while the PLL is un-
locked (when the clock may be unreliable). This feature can be disabled by setting the ClkOutUnl global
parameter, however the state CLK_OUT may then be unreliable during an unlock condition.
ClkOutUnl
PLL Locked/Unlocked
0
0
2:1 Mux
1
0
2:1 Mux
M2 pin with
M2Config[1:0] = 000, 010
PLL Clock Output
PLLClkOut
PLL Clock Output Pin
(CLK_OUT)
PLL Output
1
Figure 12. PLL Clock Output Options
Referenced Control
Parameter Definition
ClkOutUnl..............................“Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 23
ClkOutDis ..............................“M2 Configured as Output Disable” on page 19
M2Config[2:0]........................“M2 Pin Configuration (M2Config[2:0])” on page 24
DS841PP1
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