CDB5376 Datasheet, PDF (28/78 Pages) Cirrus Logic – Multichannel Seismic Evaluation System

CDB5376
input on CDB5376 can receive a lower-frequency system clock and create a synchronous higher-frequen-
cy clock using an on-board PLL.
Specification
Input Clock Frequency
Distributed Clock Synchronization
Maximum Input Clock Jitter, RMS
Value
1.024, 2.048, 4.096 MHz
8.192, 16.384, 32.768 MHz
± 240 ns
1 ns
Specification
PLL Output Clock Frequency
Maximum Output Jitter, RMS
Oscillator Type
Detector Architecture
Value
32.768 MHz
300 ps
VCXO
Phase / Frequency
The expected input clock frequency to the BNC clock input is set by the EXT_CLK jumper (J16). If no ex-
ternal clock is supplied to CDB5376, the PLL will free-run at the nominal output frequency.
The PLL on CDB5376 uses a voltage-controlled crystal oscillator (VCXO) to minimize jitter, and has a sin-
gle-gate phase/frequency detector and clock divider to minimize size and power.
Specification
Oscillator - Citizen 32.768 MHz VCXO
Surface Mount Package Type
Supply Voltage, Current
Frequency Stability, Pullability
Startup Time
Value
CSX750VBEL32.768MTR
Leadless 6-Pin, 5x7 mm
3.3 V, 11 mA
± 50 ppm, ± 90 ppm
4 ms
Specification
Phase Detector - TI LittleLogic XOR
Surface Mount Package Type
Supply Voltage, Current
Value
SN74LVC1G86DBVR
SOT23-5
3.3 V, 10 µA
Specification
Loop Filter Integrator - Linear Tech Op-Amp
Surface Mount Package Type
Supply Voltage, Current
Value
LT1783IS5
SOT23-5
3.3 V, 375 µA
Specification
Clock Divider - TI LittleLogic D-Flop
Surface Mount Package Type
Supply Voltage, Current
Value
SN74LVC2G74DCTR
SSOP8-199
3.3 V, 10 µA
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DS612DB2