CDB5376 Datasheet, PDF (26/78 Pages) Cirrus Logic – Multichannel Seismic Evaluation System

CDB5376
Pin #
1
2
3
4
5
6
7
8
Pin Name
P0.1
P0.0
GND
D+
D-
VDD
REGIN
VBUS
Assignment
SDTKI_MC
SYNC_IO
Description
Token to start CS5376A data transaction
SYNC signal from RS-485
Ground
USB differential data transceiver
USB differential data transceiver
+3.3 V power supply input
+5 V power supply input (unused on CDB5376)
USB voltage sense input
Pin #
9
10
11
12
13
14
15
16
Pin Name
/RST
C2CK
P3.0
C2D
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
Assignment
RESETz
GPIO
AIN-
AIN+
CPLD3_MC
CPLD2_MC
CPLD1_MC
CPLD0_MC
Description
Power on reset output, active low
Clock input for debug interface
General purpose I/O
Data in/out for debug interface
ADC input
ADC input
General Purpose I/O
General Purpose I/O
General Purpose I/O
General Purpose I/O
Pin #
17
18
19
20
21
22
23
24
Pin Name
P2.1
P2.0
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
Assignment
TIMEB_MC
SYNC_MC
BYP_EN
SDA_DE
SCL
SDA
SSI_MCz
MOSI_MC
Description
Time Break signal to CS5376A
SYNC signal to CS5376A
I2C bypass switch control
I2C data driver enable
I2C clock in/out
I2C data in/out
SPI chip select output, active low
SPI master out / slave in
Pin #
25
26
27
28
29
30
31
32
Pin Name
P1.1
P1.0
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
Assignment
MISO_MC
SCK1_MC
SINT_MCz
RX
TX
CLOCK_MC
SDRDY_MCz
Assignment
SPI master in / slave out
SPI serial clock
Internal VREF bypass capacitors
Serial acknowledge from CS5376A, active low
UART receiver
UART transmitter
External clock input
Data ready acknowledge from CS5376A, active low
26
DS612DB2