CDB5376 Datasheet, PDF (23/78 Pages) Cirrus Logic – Multichannel Seismic Evaluation System

CDB5376
2.3.1.1 MCLK Conversion to ACLK
The CS5376A digital filter creates the analog sampling clock used by the CS5372 ∆Σ modulators and
CS4373A test DAC (MCLK). This clock has strict jitter requirements to guarantee the accuracy of analog-
to-digital and digital-to-analog conversion, and so is carefully routed between the digital filter and modu-
lators/test DAC.
The CS3301 amplifier also receives a version of the analog sampling clock (ACLK) to run the internal
chopper stabilization circuitry, but without the strict jitter requirement since it is an analog-input/analog-
output device. To isolate the sensitive modulator/test DAC analog sampling clock route from the long
route of the amplifier clock, a 200 Ω series resistor connects the MCLK and ACLK traces together.
2.3.1.2 Configuration - SPI1 Port
Configuration of the CS5376A digital filter is through the SPI 1 port by the on-board 8051 microcontroller,
which receives commands from the PC evaluation software via the USB interface. Evaluation software
commands can write/read digital filter registers, specify digital filter coefficients and test bit stream data,
and start/stop digital filter operation. Alternately, the digital filter can automatically load configuration in-
formation from an on-board serial EEPROM.
Configuration of the digital filter is selected by the BOOT signal from dip switch #1 (S5, #1). By default
the BOOT signal is set low (S5, #1 - LO) to indicate configuration information is written by the microcon-
troller. If BOOT is set high (S5, #1 - HI), the digital filter attempts to automatically read configuration in-
formation from the serial EEPROM after reset. The serial EEPROM on CDB5376 is provided for custom
programming convenience only and is not directly supported by the PC evaluation software or microcon-
troller firmware.
2.3.2 Interface CPLD
A Xilinx CPLD is included on CDB5376 (XCR3128XL-10VQ100I) as an interface between the CS5376A
digital filter and the microcontroller. By default the CPLD only passes through the interface signals, but
can be reprogrammed to disconnect the on-board 8051 microcontroller and connect to another external
microcontroller through the spare dual-row headers. Control signals taken off the CDB5376 board to an
external microcontroller should pair with a ground return wire to maintain signal integrity.
Free software tools and an inexpensive hardware programmer for the Xilinx CPLD are available from the
internet (http://www.xilinx.com). The hardware programmer interfaces with the Xilinx JTAG programming
port (J39) on CDB5376. Note that early versions of the Xilinx WebPack tools (7.1i SP1 and earlier) have
a bug in the JEDEC programming file for the CPLD included on CDB5376, and WebPack version 7.1i SP2
or later is required.
Included below is the default Verilog HDL file used by CDB5376 inside the interface CPLD. Comparing
the input and output definitions of this file with the CPLD schematic pinout should demonstrate how sig-
nals are selected and passed through from the microcontroller to the CS5376A digital filter. Several signal
connections to the CPLD are not defined in the default HDL file, but are routed to the CPLD on CDB5376
for convenience during custom reprogramming.
DS612DB2
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