DDC232 Datasheet, PDF (8/28 Pages) Burr-Brown (TI) – 32-Channel, Current-Input Analog-to-Digital Converter

DDC232
SBAS331C – AUGUST 2004 – REVISED SEPTEMBER 2006
DEVICE OPERATION
Basic Integration Cycle
The topology of the front end of the DDC232 is an
analog integrator as shown in Figure 3. In this
diagram, only input IN1 is shown. The input stage
consists of an operational amplifier, a selectable
feedback capacitor network (C_F), and several
switches that implement the integration cycle. The
timing relationships of all of the switches shown in
Figure 3 are illustrated in Figure 4. Figure 4
conceptualizes the operation of the integrator input
stage of the DDC232 and should not be used as an
exact timing tool for design.
See Figure 5 for the block diagrams of the reset,
integrate, wait, and convert states of the integrator
section of the DDC232. This internal switching
network is controlled externally with the convert pin
(CONV), and the system clock (CLK). For the best
noise performance, CONV must be synchronized
with the rising edge of CLK. It is recommended that
CONV toggle within ±10ns of the rising edge of CLK.
The noninverting inputs of the integrators are
connected to ground. Consequently, the DDC232
analog ground should be as clean as possible. The
internal and external capacitors (C_F), are shown in
parallel between the inverting input and output of the
operational amplifier. At the beginning of a
conversion, the switches S_A/D, S_INTA, S_INTB, S_REF1,
S_REF2, and S_RESET are set (see Figure 4).
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At the completion of an A/D conversion, the charge
on the integration capacitor (C_F) is reset with S_REF1
and S_RESET (see Figure 4 and Figure 5a). This is
done during reset. In this manner, the selected
capacitor is charged to the reference voltage, VREF.
Once the integration capacitor is charged, S_REF1 and
S_RESET are switched so that VREF is no longer
connected to the amplifier circuit while it waits to
begin integrating (see Figure 5b). With the rising
edge of CONV, S_INTA closes, which begins the
integration of side A. This process puts the integrator
stage into its integrate mode (see Figure 5c).
Charge from the input signal is collected on the
integration capacitor, causing the voltage output of
the amplifier to decrease. The falling edge of CONV
stops the integration by switching the input signal
from side A to side B (S_INTA and S_INTB). Prior to the
falling edge of CONV, the signal on side B was
converted by the A/D converter and reset during the
time that side A was integrating. With the falling edge
of CONV, side B starts integrating the input signal. At
this point, the output voltage of the side A
operational amplifier is presented to the input of the
∆Σ A/D converter (see Figure 5d).
S_REF1
3pF
VREF
Input
Current ^IN1
Photodiode
ESD
Protection
Diodes
S_INTA
S_RESET
S_INTB
50pF
25pF
12.5pF
S_{REF2 SADC1A}
Integrator A
Integrator B (same as A)
Range[2] Bit
Range[1] Bit
Range[0] Bit
To Converter
Figure 3. Basic Integration Configuration for Input 1
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