DDC232 Datasheet, PDF (16/28 Pages) Burr-Brown (TI) – 32-Channel, Current-Input Analog-to-Digital Converter

DDC232
SBAS331C – AUGUST 2004 – REVISED SEPTEMBER 2006
TIMING EXAMPLES
Continuous Mode
A few timing diagrams help illustrate the operation of
the integrate/measure state machine. These
diagrams are shown in Figure 11 through Figure 16.
Table 5 gives generalized timing specifications in
units of CLK periods for Clk_4x = 0. If Clk_4x = 1,
these values increase by a factor of 4 because of the
internal clock divider. Values (in µs) for Table 5 can
be easily found for a given CLK.
Figure 11 shows a few integration cycles beginning
with initial power-up for a cont mode example. The
top signal is CONV and is supplied by the user. The
next line indicates the current state in the state
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diagram. The following two traces show when
integrations and measurement cycles are underway.
The internal signal mbsy is shown next. Finally,
DVALID is given. As described in the data sheet,
DVALID goes active low when data is ready to be
retrieved from the DDC232. It stays low until DCLK is
taken high and then back low by the user. The text
below the DVALID pulse indicates the side of the
data available to be read and arrows help match the
data to the corresponding integration.
CONV
State 8
7
Integration
Status
m/r/az
Status
mbsy
6
Integrate B
5
Integrate A
m/r/az B
t_MRAZ
4
Integrate B
m/r/az A
5
Integrate A
m/r/az B
DVALID
t=0
Power−Up
t_CMDR
Side B
Data
Side A
Data
Figure 11. Continuous Mode Timing
Side B
Data
SYMBOL
t_MRAZ
t_CMDR
t_NCDR1
t_NCDR2
t_NCMRAZ
Table 5. Timing Specifications Generalized in CLK Periods
DESCRIPTION
Cont mode m/r/az cycle
Cont mode data ready
1st ncont mode data ready
2nd ncont mode data ready
Ncont mode m/r/az cycle
VALUE
(CLK periods with Clk_4x = 0)
Low-Power Mode
High-Speed Mode
1552 ± 2
1612 ± 2
1382 ± 2
1382 ± 2
TBD
TBD
TBD
TBD
TBD
TBD
16
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